DP8570AV datasheet(14/26 Pages) NSC

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Functional Description (Continued)

of the input data registers are loaded into the timer The

output will stay high until the counter reaches zero At zero

the output is reset The result is an output pulse whose du-

ration is equal to the input clock period times the count

value (N) loaded into the input data register This is shown

Figure 8

Pulse Width e Clock Period c N

An interrupt is generated when the zero count is reached

This can be used for one-time interrupts that are set to oc-

cur a certain amount of time in the future In this mode the

Timer StartStop bit (TSS) is automatically reset upon zero

detection This removes the need to reset TSS before start-

ing another operation

The count down operation may be temporarily suspended

either under software control by setting the Count Hold

Gate bit in the timer register high or in hardware by setting

the G0 or G1 pin high

The above discussion assumes that the timer outputs were

programmed to be non-inverting outputs (active high) If the

polarity of the output waveform is wrong for the application

the polarity can be reversed by configuring the Output Mode

to be push pull or open drain

MODE 1 RATE GENERATOR

When operating in this mode the timer will operate continu-

ously Before the timer is started its output is low When the

timer is started the input data register contents are loaded

into the counter on the negative clock edge and the output

is set high (again assuming the Output Mode Register is

programmed active high) The timer will then count down to

zero Once the zero count is reached the output goes low

for one clock period of the timer clock Then on the next

clock the counter is reloaded automatically and the count-

down repeats itself The output shown in

Figure 9 isa

waveform whose pulse width and period is determined by N

the input register value and the input clock period

Period e (N a 1) (Clock Period)

Pulse Width e Clock Period

The G0 or G1 pin and the count holdgate bit can be used

to suspend the appropriate timer countdown when either is

high Again the output polarity is controllable as in mode 0

If enabled an interrupt is generated whenever the zero

count is reached This can be used to generate a periodic

interrupt

MODE 2 SQUARE WAVE GENERATOR

This mode is also cyclic but in this case a square wave

rather than a pulse is generated The output square wave

period is determined by the value loaded into the timer input

Period e 2(N a 1) (Clock Period)

Duty Cycle e 05

When the timer is stopped the output will be low and when

the StartStop bit is set high the timer’s counter will be load-

ed on the next clock falling transition and the output will be

set high

The output will be toggled after the zero count is detected

and the counter will then be reloaded and the cycle will

continue Thus every N a 1 counts the output gets toggled

as shown in

Figure 10 Like the other modes the timer oper-

ation can be suspended either by software setting the count

holdgate bit (CHG) in the Timer Control Register or by us-

ing the gate pins An interrupt will be generated every falling

edge of the timer output if enabled

TLF8638 – 10

FIGURE 8 Typical Waveforms for Timer Mode 0

(Timer Output Programmed Active High)

TLF8638 – 11

FIGURE 9 Timing Waveforms for Timer Mode 1

(Timer Output Programmed Active High)

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