DP8570AV datasheet(16/26 Pages) NSC

16 / 26 page

Functional Description (Continued)

TABLE VII RegisterCounterRAM

Addressing for DP8570A

A0-4

Description

(Note 1) (Note 2)

CONTROL REGISTERS

Main Status Register

Timer 0 Control Register

Timer 1 Control Register

Periodic Flag Register

Interrupt Routing Register

Real Time Mode Register

Output Mode Register

Interrupt Control Register 0

Interrupt Control Register 1

COUNTERS (CLOCK CALENDAR)

1100 110 Seconds (0 – 99)

Seconds

(0 – 59)

Minutes

(0 – 59)

Hours

(1 – 12 0 – 23)

Days of

Month

(1 – 28293031)

Months

(1 – 12)

Years

(0 – 99)

Julian Date (LSB)

(0 – 99) (Note 3)

Julian Date

(0 – 3)

Day of Week

(1 – 7)

TIMER DATA REGISTERS

Timer 0 LSB

Timer 0 MSB

Timer 1 LSB

Timer 1 MSB

TIME COMPARE RAM

Sec Compare RAM

(0 – 59)

Min Compare RAM

(0 – 59)

Hours Compare

RAM

(1 – 12 0 – 23)

DOM Compare

RAM

(1 – 28293031)

Months Compare

RAM

(1 – 12)

DOW Compare RAM (1 – 7)

TIME SAVE RAM

Seconds Time Save RAM

Minutes Time Save RAM

Hours Time Save RAM

Day of Month Time Save RAM

Months Time Save RAM

RAM

RAMTest Mode Register

01 – 1F

2nd Page General Purpose RAM

Note 1

PSPage Select (Bit D7 of Main Status Register)

Note 2

RSRegister Select (Bit D6 of Main Status Register)

Note 3

The LSB counters count 0–99 until the hundreds of days counter

reaches 3 Then the LSB counters count to 65 or 66 (if a leap year) The

rollover is from 365366 to 1

MAIN STATUS REGISTER

TLF8638 – 14

The Main Status Register is always located at address 0

regardless of the register block or the page selected

This read only bit is a general interrupt status bit that is

taken directly from the interrupt pins The bit is a one when

an interrupt is pending on either the INTR pin or the MFO

pin (when configured as an interrupt) This is unlike D3 – D5

which can be set by an internal event but may not cause an

interrupt This bit is reset when the interrupt status bits in the

Main Status Register are cleared

D1 – D5

These five bits of the Main Status Register are the

main interrupt status bits Any bit may be a one when any of

the interrupts are pending Once an interrupt is asserted the

P will read this register to determine the cause These

interrupt status bits are not reset when read Except for D1

to reset an interrupt a one is written back to the correspond-

ing bit that is being tested D1 is reset whenever the PFAIL

pin e logic 1 This prevents loss of interrupt status when

reading the register in a polled mode D1 D3 – D5 are set

regardless of whether these interrupts are masked or not by

bits D6 and D7 of Interrupt Control Registers 0 and 1

D6 and D7

These bits are ReadWrite bits that control

which register block or RAM page is to be selected Bit D6

controls the register block to be accessed (see memory

map) The memory map of the clock is further divided into

two memory pages One page is the registers clock and

timers and the second page contains 31 bytes of general

purpose RAM The page selection is determined by bit D7

DP8570AV 数据表(PDF) 16 Page - National Semiconductor (TI)

DP8570AV 数据表(HTML) 16 Page - National Semiconductor (TI)

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26

数据表下载

链接网址

DP8570AV 数据表(PDF) 16 Page - National Semiconductor (TI)

DP8570AV 数据表(HTML) 16 Page - National Semiconductor (TI)

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26

数据表 下载

链接网址

数据表下载