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P89LPC921 数据表(PDF) 26 Page - NXP Semiconductors |
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P89LPC921 数据表(HTML) 26 Page - NXP Semiconductors |
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26 / 45 page ![]() Philips Semiconductors P89LPC920/921/922 8-bit microcontrollers with two-clock 80C51 core Product data Rev. 06 — 21 November 2003 26 of 45 9397 750 12285 © Koninklijke Philips Electronics N.V. 2003. All rights reserved. 8.19 I2C-bus serial interface I2C-bus uses two wires (SDA and SCL) to transfer information between devices connected to the bus, and it has the following features: • Bidirectional data transfer between masters and slaves • Multimaster bus (no central master) • Arbitration between simultaneously transmitting masters without corruption of serial data on the bus • Serial clock synchronization allows devices with different bit rates to communicate via one serial bus • Serial clock synchronization can be used as a handshake mechanism to suspend and resume serial transfer • The I2C-bus may be used for test and diagnostic purposes. A typical I2C-bus configuration is shown in Figure 8. The P89LPC920/921/922 device provides a byte-oriented I2C-bus interface that supports data transfers up to 400 kHz. Fig 8. I2C-bus configuration. OTHER DEVICE WITH I2C-BUS INTERFACE SDA SCL RP RP OTHER DEVICE WITH I2C-BUS INTERFACE P1.3/SDA P1.2/SCL P89LPC920/921/922 I2C-BUS 002aaa420 |
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