LP8553

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SNVS701B – SEPTEMBER 2011 – REVISED JANUARY 2014

Over-Current Protection

LP8553 has detection for too-high loading on the boost converter. When over-current fault is detected, the

LP8553 will shut down.

Fault is cleared by setting EN pin low or by reading the fault register.

Device Thermal Regulation

LP8553 has an internal temperature sensor which can be used to measure the junction temperature of the

device and protect the device from overheating. During thermal regulation, LED PWM is reduced by 2% of full

scale per °C whenever the temperature threshold is reached. Temperature regulation is enabled automatically

when chip is enabled. 11-bit temperature value can be read from Temp MSB and Temp LSB registers, MSB

should be read first. Temperature limit can be programmed in EEPROM as shown in the following table.

Thermal regulation function does not generate fault signal.

TEMP_LIM[1:0]

Over-Temp Limit (°C)

00

OFF

01

110

10

120

11

130

Thermal Shutdown

If the LP8553 reaches thermal shutdown temperature (150°C ) the LED outputs and boost will shut down to

protect it from damage. Also the fault pin will be pulled down to indicate the fault state. Device will activate again

when temperature drops below 130°C degrees.

Fault is cleared by setting EN pin low or by reading the fault register.

I

Interface Bus Overview

the device. This protocol uses a two-wire interface for bidirectional communications between the IC's connected

to the bus. The two interface lines are the Serial Data Line (SDA) and the Serial Clock Line (SCLK). These lines

should be connected to a positive supply, via a pull-up resistor and remain HIGH even when the bus is idle.

Every device on the bus is assigned a unique address and acts as either a Master or a Slave depending on

whether it generates or receives the SCLK. The LP8553 is always a slave device.

Data Transactions

One data bit is transferred during each clock pulse. Data is sampled during the high state of the serial clock

SCLK. Consequently, throughout the clock’s high period, the data should remain stable. Any changes on the

SDA line during the high state of the SCLK and in the middle of a transaction, aborts the current transaction.

New data should be sent during the low SCLK state. This protocol permits a single data line to transfer both

command/control information and data using the synchronous serial clock.

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Product Folder Links: LP8553