SDA

SCL

Start

Condition

Stop

Condition

S

P

SCL

2

1

8

7

3 - 6

9

S

Start

Condition

Acknowledgment

Signal From Receiver

Data Output

by

Receiver

Data Output

by

Transmitter

Transmitter Stays Off the

Bus During the

Acknowledgment Clock

SDA

SCL

Data Line

Stable:

Data Valid

Change

of Data

Allowed

LP8553

SNVS701B – SEPTEMBER 2011 – REVISED JANUARY 2014

www.ti.com

Figure 21. Bit Transfer

Each data transaction is composed of a Start Condition, a number of byte transfers (set by the software) and a

Stop Condition to terminate the transaction. Every byte written to the SDA bus must be 8 bits long and is

transferred with the most significant bit first. After each byte, an Acknowledge signal must follow. The following

sections provide further details of this process.

Figure 22. Start and Stop

The Master device on the bus always generates the Start and Stop Conditions (control codes). After a Start

Condition is generated, the bus is considered busy and it retains this status until a certain time after a Stop

Condition is generated. A high-to-low transition of the data line (SDA) while the clock (SCLK) is high indicates a

Start Condition. A low-to-high transition of the SDA line while the SCLK is high indicates a Stop Condition.

Figure 23. Start and Stop Conditions

In addition to the first Start Condition, a repeated Start Condition can be generated in the middle of a transaction.

This allows another device to be accessed, or a register read cycle.

Acknowledge Cycle

The Acknowledge Cycle consists of two signals: the acknowledge clock pulse the master sends with each byte

transferred, and the acknowledge signal sent by the receiving device.

22

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