LP8553 datasheet(13/42 Pages) TI1

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5MHz internal

oscillator

PLL[12:0]

PWM generation

PWM_FREQ[4:0]

or External

set resistor RFSET

VBOOST

LED Drivers 1-4

Divider

1/N

5 MHz...40 MHz

PSPWM 0/1

Boost

Filter

VCO

Counter

1/N

PLL

VSYNC

60 Hz

EN_VSYNC

Phase

Detector

State machine,

PWM input, internal

timings, Slope etc.

BOOST_FREQ

N = 4, 8, 16, 32

PWM_RESOLUTION[1:0]

LP8553

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SNVS701B – SEPTEMBER 2011 – REVISED JANUARY 2014

Clock Generation

LP8553 has an internal 5 MHz oscillator which is used for clocking the boost converter, state machine, PWM

input duty cycle measurement, internal timings such as slope time for output brightness changes.

An internal clock can be used for generating the PWM output frequency. In this case the 5 MHz clock can be

multiplied with the internal PLL to achieve higher resolution. The higher the clock frequency for PWM generation

block, the higher the resolution but the tradeoff is higher IQ of the part. Clock multiplication is set with

<PWM_RESOLUTION[1:0]> EEPROM Bits.

The PLL can also be used for generating the required PWM generation clock from the VSYNC signal. This makes

sure that the LED output PWM is always synchronized to the VSYNC signal and there is no clock variation

between LCD display video update and the LED backlight output frequency. Also HSYNC signal up to 55 kHz can

be used.

PLL has internal counter which has 13-bit control <PLL[12:0]> to achieve correct output clock frequency based

on the VSYNC frequency.

For the PLL it can take couple of seconds to synchronize to 60 Hz VSYNC signal in startup and before this correct

PWM clock frequency is generated from internal oscillator. FILTER pin component selection affects the time it

takes from the PLL to lock to VSYNC signal.

Special logic is implemented for allowing steady clock frequency even if there are missing VSYNC pulses. In case

pulses are randomly left out, the LP8553 can generate the pulses internally while keeping the same PWM output

frequency. When VSYNC pulses are available again, the internal logic will automatically switch to the external

VSYNC clock without glitch.

Figure 15. Principle of the Clock Generation

Brightness Control Methods

LP8553 controls the brightness of the backlight with PWM. PWM control is received either from PWM input pin or

from I2C register bits. The PWM source selection is done with <BRT_MODE[1:0]> bits as follows:

BRT_MODE[1]

BRT_MODE[0]

PWM source

PWM input pin duty cycle control. Default.

PWM input pin duty cycle control.

Brightness register

PWM direct control (PWM in = PWM out)

PWM Input Duty Cycle

With PWM input pin duty-cycle control the output PWM is controlled by PWM input duty cycle. PWM detector

block measures the duty cycle in the PWM pin and uses this 13-bit value to generate the output PWM. Output

PWM can have different frequency than input in this mode and also phase shift PWM mode can be used. Slope

and dither are effective in this mode. PWM input resolution is defined by the input PWM clock frequency.

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