PCM1802

SLES023B – DECEMBER 2001 – REVISED MARCH 2002

19

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PRINCIPLES OF OPERATION

interface timing (continued)

BCK

FSYNC

LRCK

DOUT

t(CKFS)

t(BCKH)

t(BCKL)

t(CKLR)

t(LRCP)

t(BCKP)

t(CKDO)

t(LRDO)

0.5 VDD

0.5 VDD

0.5 VDD

0.5 VDD

t(FSYP)

PARAMETER

MIN

TYP

MAX

UNIT

t(BCKP)

BCK period

150

1/(64 fS)

1200

ns

t(BCKH)

BCK pulse width high

75

600

ns

t(BCKL)

BCK pulse width low

75

600

ns

t(CKLR)

Delay time BCK falling edge to LRCK valid

–10

20

ns

t(LRCP)

LRCK period

10

1/ fS

80

µs

t(CKFS)

Delay time BCK falling edge to FSYNC valid

–10

20

ns

t(FSYP)

FSYNC period

5

1/(2 fS)

40

µs

t(CKDO)

Delay time, BCK falling edge to DOUT valid

–10

20

ns

t(LRDO)

Delay time, LRCK edge to DOUT valid

–10

20

ns

tr

Rise time of all signals

10

ns

tf

Fall time of all signals

10

ns

NOTE: Timing measurement reference level is (VIH/VIL) / 2. Rise and fall times are measured from 10% to 90% of IN/OUT signal swing. Load

capacitance of all signals is 20 pF.

Figure 27. Audio Data Interface Timing (Master Mode: FSYNC, LRCK, BCK Work as Outputs)