PCM1802

SLES023B – DECEMBER 2001 – REVISED MARCH 2002

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APPLICATION INFORMATION

board design and layout considerations

The digital and analog power supply lines to the PCM1802 should be bypassed to the corresponding ground

pins with 0.1-

µF ceramic and 10-µF tantalum capacitors as close to the pins as possible to maximize the

dynamic performance of the ADC.

AGND, DGND pins

To maximize the dynamic performance of the PCM1802, the analog and digital grounds are not connected

internally. These grounds should have very low impedance to avoid digital noise feeding back into the analog

ground. They should be connected directly to each other under the parts to reduce the potential noise problem.

A 1-

µF capacitor is recommended as an ac-coupling capacitor which gives 8-Hz cutoff frequency. If a higher

A 0.1-

pin to reduce the dynamic errors on ADC references.

10-

between VCC and VREF2 for using a noisy analog power supply. These capacitors and resistor are not required

the dynamic errors on ADC references. Full-scale input level is affected by this 1-k

Ω resistor and decreases

by 3%.

DOUT pin

The DOUT pin has enough load drive capability, but locating a buffer near the PCM1802 and minimizing load

capacitance is recommended if the DOUT line is long, in order to minimize the digital-analog crosstalk and

maximize the dynamic performance of the ADC.

system clock

The quality of the system clock can influence dynamic performance, as the PCM1802 operates based on the

system clock. In slave mode, it may be necessary to consider the system-clock duty cycle, jitter, and the time

difference between the system clock transition and the BCK or LRCK transition.