PCM1802

SLES023B – DECEMBER 2001 – REVISED MARCH 2002

20

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PRINCIPLES OF OPERATION

synchronization with digital audio system

In slave mode, the PCM1802 operates under LRCK, synchronized with system clock SCKI. The PCM1802 does

not need a specific phase relationship between LRCK and SCKI, but does require the synchronization of LRCK

and SCKI.

If the relationship between LRCK and SCKI changes more than

±6 BCKs for 64 BCK/frame (±5 BCKs for

48 BCK/frame) during one sample period due to LRCK or SCKI jitter, internal operation of the ADC halts within

In the case of changes less than

±5 BCKs for 64 BCK/frame (±4 BCKs for 48 BCK/frame), resynchronization

does not occur.

Figure 28 illustrates digital output response for loss of synchronization and resynchronization. During undefined

data, some noise might be generated in the audio signal. Also, the transition of normal to undefined data and

undefined or zero data to normal creates a data discontinuity in the digital output, which can generate some

noise in the audio signal.

It is recommended to set PDWN low to get stable analog performance when the sampling rate, interface mode,

data format, or oversampling control is changed.

1/fS

32/fS

NORMAL DATA

ZERO DATA

UNDEFINED

DATA

NORMAL DATA

SYNCHRONOUS

ASYNCHRONOUS

SYNCHRONOUS

Resynchronization

Synchronization Lost

DOUT

State of Synchronization

Figure 28. ADC Digital Output for Loss of Synchronization and Resynchronization

power down, LCF bypass, oversampling control

PDWN (pin 7) controls the entire ADC operation. During power-down mode, both the supply current for the

analog portion and the clock signal for the digital portion are shut down, and power dissipation is minimized.

Also, DOUT (pin 12) is disabled and no system clock is accepted during power-down mode.

Table 4. Power-Down Control

PDWN

Power-down mode

LOW

Power-down mode

HIGH

Normal operation mode

The built-in function for dc component rejection can be bypassed using the BYPAS (pin 8) control. In bypass

mode, the dc components of the analog input signal, internal dc offset, etc., are also converted and included

in the digital output data.

Table 5. LCF Bypass Control

BYPAS

LCF (low-cut filter) mode

LOW

Normal (no dc component on DOUT) mode

HIGH

Bypass (dc component on DOUT) mode