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TP3402 数据表(PDF) 12 Page - National Semiconductor (TI) |
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TP3402 数据表(HTML) 12 Page - National Semiconductor (TI) |
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12 / 16 page  Timing Characteristics Unless otherwise noted VCC ea5V g5% TA e 0 Cto70 C Typical characteristics are specified at VCC e 5V TA e 25 C All signals are referenced to GND Symbol Parameter Conditions Min Typ Max Units MASTER CLOCK INPUT SPECIFICATIONS FMCK Master Clock Frequency 2048 MHz Master Clock Tolerance Measured Relative to the Slave MCLK b 100 a 100 ppm Master Clock Input Jitter 2048 MHz Input 18 kHz k f k 200 kHz 200 ns pk-pk tWMH Clock Pulse Width VIH e VCC b 05V 190 ns tWML Hi Low for MCLK VIL e 05V tMR Rise and Fall Time Used as a Logic Input 15 ns tMF of MCLK B CHANNEL INTERFACE (Figure 10) FBCK Bit Clock Frequency Master Mode Only 2048 MHz tWBH Clock Pulse Width VIH e 22V 190 ns tWBL Hi Low for BCLK VIL e 07V tBR Rise and Fall Time Master Mode requirement for BCLK 15 ns Source tBF of BCLK tSFB Set-Up Time FSa and Master Mode Only 70 ns FSb to BCLK Low tHCFL Hold Time BCLK Low to Master Mode Only 100 ns FSa and FSb Low tWBH Output Pulse Width Slave Mode Only 195 ns tWBL High and Low for BCLK Load e 2 LSTTL Inputs Plus 50 pF tDCF Delay Time BCLK High to Slave Mode Only 115 ns FSa FSb and FSc Transitions Load e 2 LSTTL Inputs Plus 50 pF tSBC Set Up Time BX Valid 30 ns to BCLK Low tHCB Hold Time BCLK Low to 50 ns BX Invalid tDCB Delay Time BCLK High Load e 2 LSTTL Inputs Plus 100 pF 160 ns to Br Valid tDCBZ Delay Time BCLK Low to Slave Mode Only 60 220 ns Br High-Impedance tDCT Delay Time BCLK High Load e 2 LSTTL Inputs Plus 100 pF 180 ns to TSr Low tDCTZ Delay Time BCLK Low to 60 185 ns TSr High-Impedance tSMBC Set-Up Time MBS Master Mode Only 60 ns to BCLK Low (Note 1) (TP3401 and TP3403 only) tWMBH Width of MBS Input Master Mode Only 125 m s High (TP3401 and TP3403 only) Note 1 MBS transitions may occur anywhere in the Frame and require no specific relationship to FSa or FSb 12 |
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