TP3402 datasheet(14/16 Pages) NSC

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Definitions and Timing Conventions

DEFINITIONS

VIH

VIH is the dc input level above which

an input level is guaranteed to appear

as a logical one This parameter is to

be measured by performing a function-

al test at reduced clock speeds and

nominal timing (ie not minimum setup

and hold times or output strobes) with

the high level of all driving signals set

to VIH and maximum supply voltages

applied to the device

VIL

VIL is the dc input level below which

an input level is guaranteed to appear

as a logical zero to the device This pa-

rameter is measured in the same man-

ner as VIH but with all driving signal low

levels set to VIL and minimum supply

voltages applied to the device

VOH

VOH is the minimum dc output level to

which an output placed in a logical one

state will converge when loaded at the

maximum specified load current

VOL

VOL is the maximum dc output level to

which an output placed in a logical zero

state will converge when loaded at the

maximum specified load current

Threshold Region

The threshold region is the range of in-

put voltages between VIL and VIH

Valid Signal

A signal is Valid if it is in one of the

valid logic states (ie above VIH or be-

low VIL) In timing specifications a sig-

nal is deemed valid at the instant it en-

ters a valid state

Invalid Signal

A signal is Invalid if it is not in a valid

logic state ie when it is in the thresh-

old region between VIL and VIH In tim-

ing specifications a signal is deemed

invalid at the instant it enters the

threshold region

TIMING CONVENTIONS

For the purpose of this timing specification the following

conventions apply

Input Signals

All input signals may be characterized

as VL e 04V VIH e 24V tR k 10 ns

tF k 10 ns

Period

The period of clock signal is designat-

ed at tPxx where xx represents the

mnemonic of the clock signal being

specified

Rise Time

Rise times are designated at tRyy

where yy represents a mnemonic of

the signal whose rise time is being

specified tRyy is measured from VIL to

VIH

Fall Time

Fall times are designated as tFyy

where yy represents a mnemonic of

the signal whose fall time is being

specified tFyy is measured from VIH to

VIL

Pulse Width High

The high width is designated as tWzzH

where zz represents the mnemonic of

the input or output signal whose pulse

width is being specified High pulse

widths are measured from VIH to VIH

Pulse Width Low

The low pulse width is designed as

tWzzL where zz represents the mne-

monic of the input or output signal

whose pulse width is being specified

Low pulse widths are measured from

VIL to VIL

Setup Time

Setup times are designated as tSwwxx

where ww represents the mnemonic of

the input signal whose setup time is be-

ing specified relative to a clock or

strobe input represented by mnemonic

xx Setup times are measured from the

ww Valid to xx Invalid

Hold Time

Hold times are designated as tHxxww

where ww represents the mnemonic of

the input signal whose hold time is be-

ing specified relative to a clock or

strobe input represented by mnemonic

xx Hold times are measured from xx

Valid to ww invalid

Delay Time

Delay times are designated as tDxxyy

lHlL where xx represents the mne-

monic of the input reference signal and

yy represents the mnemonic of the out-

put signal whose timing is being speci-

fied relative to xx The mnemonic may

optionally be terminated by an H or L to

specifiy the high going or low going

transition of the output signal Maxi-

mum delay times are measured from xx

Valid to yy Valid Minimum delay times

are measured from xx Valid to yy inval-

id This parameter is tested under the

load conditions specified in the Condi-

tions column of the Timing Specifica-

tion section of this data sheet

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