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TP3402 数据表(PDF) 13 Page - National Semiconductor (TI) |
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TP3402 数据表(HTML) 13 Page - National Semiconductor (TI) |
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13 / 16 page  Timing Characteristics (Continued) Unless otherwise noted VCC ea5V g5% TA e 0 Cto70 C Typical characteristics are specified at VCC e 5V TA e 25 C All signals are referenced to GND Symbol Parameter Conditions Min Max Units D CHANNEL INTERFACE (Figure 11 12) tSDDC Set Up Time DX 100 ns Valid to DCLK Low tHCD Hold Time DCLK Low 100 ns to DX Invalid tDDCD Delay Time DCLK High to Load e 100 pF 220 ns Dr Data Valid a 2 LSTTL Inputs tSDCB Set-Up Time DCLK Master Mode 50 ns Transitions to BCLK High Only tHBDC Hold Time BCLK High Master Mode 50 ns to DCLK Transitions Only tSDCF Set-Up Time DCLK Master Mode 70 ns Transitions to FSa HIgh Only tDDED Delay Time DEN High Load e 100 pF a 200 ns to Dr Valid 2 LSTTL Inputs tSDEB Set-Up Time DEN to 100 ns BCLK Low tSDBC Set-Up Time Dx 50 ns to BCLK Low tHBCD Hold Time BCLK 50 ns Low to Dx Invalid tDBCD Delay Time BCLK Load e 100 pF 190 ns High to Dr Valid a 2 LSSTL Inputs tDCDZ Delay Time DEN 140 ns Low to Dr High Impedance CONTROL INTERFACE (Figure 13) tCH CCLK High Duration 250 ns tCL CCLK Low Duration 250 ns tSIC Setup Time CI 100 ns Valid to CCLK High tHCI Hold Time CCLK High 0 ns to CI Invalid tSSC Setup Time from CS 200 ns Low to CCLK High tHCS Hold Time from CCLK 10 ns Low to CS tDCO Delay Time from CCLK Low Load e 100 pF 150 ns to C0 Data Valid a 2 LSTTL Inputs tDSO Delay Time from CS 1st Bit Only 100 ns Low to CO Valid tDSZ Delay Time from CS High 100 ns to CO High Impedance tDCI Delay Time from CCLK1 120 ns High to INT High Impedance 13 |
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