CS5505-ASZ datasheet(7/40 Pages) CIRRUS

7 / 40 page

3.3V SWITCHING CHARACTERISTICS (TA = TMIN to TMAX VA+ = 5V ± 10%;

VD+ = 3.3V

± 5%; VA- = -5V ± 10%; Input Levels: Logic 0 = 0V, Logic 1 = VD+; CL = 50 pF.) (Note 2)

Parameter

Symbol

Min

Typ

Max

Units

Master Clock Frequency:

Internal Oscillator:

-A,B

-S

External Clock:

XIN

fclk

30.0

32.768

53.0

34.0

163

kHz

Master Clock Duty Cycle

Rise Times:

Any Digital Input

(Note 10)

Any Digital Output

trise

1.0

µs

Fall Times:

Any Digital Input

(Note 10)

Any Digital Output

tfall

1.0

µs

Start-Up

Power-On Reset Period

(Note 11)

tres

-10

Oscillator Start-up Time

XTAL=32.768 kHz

(Note 12)

tosu

500

Wake-up Period

(Note 13)

twup

1800/fclk

-s

Calibration

CONV Pulse Width (CAL = 1)

(Note 14)

tccw

100

CONV and CAL High to Start of Calibration

tscl

2/fclk+200

Start of Calibration to End of Calibration

tcal

3246/fclk

-s

Conversion

Set Up Time

A0, A1 to CONV High

tsac

Hold Time

A0, A1 after CONV High

thca

100

CONV Pulse Width

tcpw

100

CONV High to Start of Conversion

tscn

2/fclk+200

Set Up Time

BP/UP stable prior to DRDY falling

tbus

82/fclk

Hold Time

BP/UP stable after DRDY falls

tbuh

Start of Conversion to End of Conversion

(Note 15)

tcon

1624/fclk

-s

CS5505/6/7/8

DS59F4

CS5505/6/7/8

DS59F5

CS5505-ASZ 数据表(PDF) 7 Page - Cirrus Logic

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