CS5505-ASZ datasheet(22/40 Pages) CIRRUS

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Synchronous External-Clocking Mode

The serial port operates in the SEC mode when

the M/SLP pin is connected to the DGND pin.

SDATA is the output pin for the serial data.

When CS goes low after new data becomes

available (DRDY goes low), the SDATA pin

comes out of Hi-Z with the MSB data bit pre-

sent. SCLK is the input pin for the serial clock

in the SEC mode. If the MSB data bit is on the

SDATA pin, the first rising edge of SCLK en-

ables the shifting mechanism. This allows the

falling edges of SCLK to shift subsequent data

bits out of the port. Note that if the MSB data

bit is output and the SCLK signal is high, the

first falling edge of SCLK will be ignored be-

cause the shifting mechanism has not become

activated. After the first rising edge of SCLK,

each subsequent falling edge will shift out the

serial data. Once the LSB is present, the falling

edge of SCLK will cause the SDATA output to

go to Hi-Z and DRDY to return high. The serial

port register will be updated with a new data

word upon the completion of another conversion

if the serial port has been emptied, or if the CS

is inactive (high).

CS can be operated asynchronously to the

DRDY signal. The DRDY signal need not be

monitored as long as the CS signal is taken low

for at least two XIN clock cycles plus 200 ns

prior to SCLK being toggled. This ensures that

CS has gained control over the serial port.

Sleep Mode

The CS5505/6/7/8 devices offer two methods of

putting the device into a SLEEP condition to

conserve power. Calibration words will be re-

tained in SRAM during either sleep condition.

The M/SLP pin can be put into the SLEEP

threshold to lower the operating power used by

the device to about 1% of nominal. Alternately,

the clock into the XIN pin can be stopped. This

will lower the power consumed by the converter

to about 30% of nominal.

In both cases, the

converter must go through a wake-up sequence

prior to conversions being initiated. This wake-

up sequence includes the 10 msec. (typ.)

power-on-reset delay, the start-up of the oscilla-

tor (unless an external clock is used), and the

1800 clock cycle wake-up delay after the clock

begins.

When coming out of the sleep condi-

tion, the converter will latch the A0 and A1

inputs.

Figure 13 illustrates how to use a gate and resis-

tors to bias the M/SLP pin into the SLEEP

threshold region when using the converter in the

SSC mode. To use the SEC mode return resistor

R1 to DGND instead of the supply.

When in

the SEC mode configuration the CS5505/6/7/8

will enter the SLEEP threshold when the logic

control input is a logic 1 (VD+). Note that large

resistors can be used to conserve power while in

sleep. The input leakage of the pin is typically

less than 1

µA even at 125 °C, although the

worst case specification tables indicate a leakage

of 10

µA maximum.

Power Supplies and Grounding

The analog and digital supply pins to the

CS5505/6/7/8 are brought out on separate pins to

minimize noise coupling between the analog and

digital sections of the chip. Note that there is no

M/SLP

CS5505/6/7/8

’1’ = SSC Mode

’0’ = SLEEP

Control

Input

VD+

* Tie R to DGND for SEC mode; control input

logic inverts.

0.01

µF

R = 499k, V + = 5V; R = 590k, V + = 3.3V

499k

Figure 13. Sleep Threshold Control

CS5505/6/7/8

DS59F4

CS5505/6/7/8

DS59F5

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