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QL8050 数据表(PDF) 39 Page - List of Unclassifed Manufacturers

部件名 QL8050
功能描述  LOW POWER FPGA COMBINING PERFORMANCE DENSITY AND EMBEDED RAM
PDF  49 Pages
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制造商  ETC [List of Unclassifed Manufacturers]
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标志 ETC - List of Unclassifed Manufacturers

QL8050 数据表(HTML) 39 Page - List of Unclassifed Manufacturers

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Preliminary

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All unused, general purpose I/O pins can be tied to V
CC, GND, or HIZ (high impedance) internally
using the Configuration Editor. This option is given in the bottom-right corner of the placement
window. To use the Placement Editor, choose Constraint
> Fix Placement in the Option pull-
down menu of SpDE.
The rest of the pins should be terminated at the board level in the manner presented in
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PLLOUT<x>a
a. x represents a number.
Unused PLL output pins must be connected to either VCC or GND so that their associated
input buffer never floats. Utilized PLL output pins that route the PLL clock outside of the
chip should not be tied to either VCC or GND.
IOCTRL<y>b
b. y represents an aphabetical character.
There is an internal pulldown resistor to Ground on this pin. This pin should be tied to
Ground if it is not used. For backwards compatibility with Eclipse, it can be tied to Vcc or
Ground. If tied to Vcc, it will draw no more than 20 µA per IOCTRL pin due to the pulldown
resistor.
CLK/PLLIN<x>
Any unused clock pins should be connected to VCC or GND.
PLLRST<x>
If a PLL module is not used, then the associated PLLRST<x> must be connected to VCC,
under normal operation use it as needed.
INREF<y>
If an I/O bank does not require the use of INREF signal the pin should be connected to
GND.
Eclipse-II
QL8325-7PQ208C



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