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QL8050 数据表(PDF) 9 Page - List of Unclassifed Manufacturers |
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QL8050 数据表(HTML) 9 Page - List of Unclassifed Manufacturers |
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9 / 49 page  4XLFN/RJLF &RUSRUDWLRQ ZZZTXLFNORJLFFRP (FOLSVH,,)DPLO\ 'DWD 6KHHW 5HY % Preliminary NOTE: +) VWDQGV IRU KLJK IUHTXHQF\ DQG /) VWDQGV IRU ORZIUHTXHQF\ The input frequency can range from 16 MHz to 300 MHz, while output frequency ranges from 25 MHz to 250 MHz. When you add PLLs to your top-level design, be sure that the PLL mode matches your desired input and output frequencies. 3//6LJQDOV 7DEOH summarizes the key signals in QuickLogic's PLLs. NOTE: %HFDXVH 3//&/.B,1 DQG 3//B5(6(7 VLJQDOV KDYH3//B,13$' DQG 3//3$'B287 KDV 2873$'\RXGR QRWKDYH WRDGG DGGLWLRQDO SDGV WR\RXU GHVLJQ 7DEOH 3//0RGH )UHTXHQFLHV 3// 0RGHO 2XWSXW )UHTXHQF\ ,QSXW)UHTXHQF\ 5DQJH 2XWSXW )UHTXHQF\ 5DQJH PLL_HF Same as input 66 MHz–150 MHz 66 MHz–150 MHz PLL_LF Same as input 25 MHz–133 MHz 25 MHz–133 MHz PLL_MULT2HF 2x 50 MHz–125 MHz 100 MHz–250 MHz PLL_MULT2LF 2x 16 MHz–50 MHz 32 MHz–100 MHz PLL_DIV2HF 1/2x 100 MHz–250 MHz 50 MHz–125 MHz PLL_DIV2LF 1/2x 50 MHz–100 MHz 25 MHz–50 MHz PLL_MULT4 4x 16 MHz–40 MHz 64 MHz–160 MHz PLL_DIV4 1/4x 100 MHz–300 MHz 25 MHz–75 MHz 7DEOH 4XLFN/RJLF3//6LJQDOV 6LJQDO1DPH 'HVFULSWLRQ PLLCLK_IN Input clock signal PLL_RESET Active High Reset If PLL_RESET is asserted, then CLKNET_OUT and PLLPAD_OUT are reset to 0. This signal must be asserted and then released in order for the LOCK_DETECT to work. ONn_OFFCHIP PLL output This signal selects whether the PLL will drive the internal clock network or be used off-chip. This is a static signal, not a dynamic signal. Tied to GND = outgoing signal drives internal gates. Tied to VCC = outgoing signal used off-chip. CLKNET_OUT Out to internal gates This signal bypasses the PLL logic before driving the internal gates. Note that this signal cannot be used in the same quadrant where the PLL signal is used (PLLCLK_OUT). PLLCLK_OUT Out from PLL to internal gates This signal can drive the internal gates after going through the PLL. For this to work, ONn_OFFCHIP must be tied to GND. PLLPAD_OUT Out to off-chip This outgoing signal is used off-chip. For this to work, ONn_OFFCHIP signal must be tied to VCC. LOCK_DETECT Active High Lock detection signal NOTE: For simulation purposes, this signal gets asserted after 10 clock cycles. However, it can take a maximum of 200 clock cycles to sync with the input clock upon release of the RESET signal. |
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