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QL8050 数据表(PDF) 7 Page - List of Unclassifed Manufacturers

部件名 QL8050
功能描述  LOW POWER FPGA COMBINING PERFORMANCE DENSITY AND EMBEDED RAM
PDF  49 Pages
Scroll/Zoom Zoom In 100%  Zoom Out
制造商  ETC [List of Unclassifed Manufacturers]
网页  
标志 ETC - List of Unclassifed Manufacturers

QL8050 数据表(HTML) 7 Page - List of Unclassifed Manufacturers

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Preliminary

The modes for the ECU block are dynamically re-programmable through the programmable logic.
NOTE:
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Instead of requiring extra components, designers simply need to instantiate one of the pre-
configured models (described in this section). The QuickLogic built-in PLLs support a wider range
of frequencies than many other PLLs. These PLLs also have the ability to support different ranges
of frequency multiplications or divisions, driving the device at a faster or slower rate than the
incoming clock frequency. When PLLs are cascaded, the clock signal must be routed off-chip
through the PLLPAD_OUT pin prior to routing into another PLL; internal routing cannot be used
for cascading PLLs.
PLLs achieve a very short clock-to-out time—generally less than 3 ns. This low clock-to-out time
is achieved by the PLL subtracting the clock tree delay through the feedback path, effectively
making the clock tree delay zero.
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a. tPD, tSU and tCO do not include routing paths in/out of the ECU block.
6 6 6
W3'
W68
W&2
0
0
0
Multiply
6.6 ns max
0
0
1
Multiply-Add
8.8 ns max
0
1
0
Accumulateb
b. Internal feedback path in ECU restricts max clk frequency to 238 MHz.
3.9 ns min
1.2 ns max
0
1
1
Add
3.1 ns max
1
0
0
Multiply (registered)c
c. B [15:0] set to zero.
9.6 ns min
1.2 ns max
1
0
1
Multiply- Add (registered)
9.6 ns min
1.2 ns max
1
1
0
Multiply - Accumulate
9.6 ns min
1.2 ns max
1
1
1
Add (registered)
3.9 ns min
1.2 ns max



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