DP7261

© NIDEC COPAL ELECTRONICS CORP.

7

Doc. No. MD-2122 Rev. E

Characteristics subject to change without notice

Figure 2. HOLD

¯¯¯¯¯ Timing

INSTRUCTION AND REGISTER

DESCRIPTION

DEVICE TYPE / ADDRESS BYTE

The first byte sent to the DP7261 from the master/

processor is called the Device Address Byte. The

most significant four bits of the Device Type address

are a device type identifier. These bits for the

DP7261 are fixed at 0101[B] (refer to Table 1).

The two least significant bits in the slave address

byte, A1 - A0, are the internal slave address and must

match the physical device address which is defined by

the state of the A1 - A0 input pins for the DP7261 to

successfully continue the command sequence. Only

the device which slave address matches the incoming

device address sent by the master executes the

instruction. The A1 - A0 inputs can be actively driven

remaining two bits in the device address byte must be

set to 0.

INSTRUCTION BYTE

The next byte sent to the DP7261 contains the

instruction and register pointer information. The four

most significant bits used provide the instruction

opcode I3 - I0. The R1 and R0 bits point to one of the

four data registers of each associated potentiometer.

The least two significant bits point to one of two Wiper

Control Registers. The format is shown in Table 2.

Data Register Selection

Data Register Selected

R1

R0

DR0

0

0

DR1

0

1

Table 1. Identification Byte Format

Table 2. Instruction Byte Format

ID3

ID2

ID1

ID0

A3

A2

A1

A0

0101

(MSB)

(LSB)

Device Type

Identifier

Slave Address

I3

I2

I1

I0

R1

R0

P1

P0

(MSB)

(LSB)

Instruction

Data Register

WCR/Pot Selection

Opcode

Selection

CS

SCK

HOLD

SO

tCD

tHD

tHD

tCD

tLZ

tHZ

HIGH IMPEDANCE