DP7261

© NIDEC COPAL ELECTRONICS CORP.

9

Doc. No. MD-2122 Rev. E

Characteristics subject to change without notice

The basic sequence of the three byte instructions is

illustrated in Figure 8. These three-byte instructions

exchange data between the WCR and one of the Data

Registers. The WCR controls the position of the wiper.

The response of the wiper to this action will be

wiper position), to a Data Register is a write to non-

complete. The transfer can occur between one of the

potentiometers and one of its associated registers; or

the transfer can occur between both potentiometers

and one associated register.

Four instructions require a two-byte sequence to

complete, as illustrated in Figure 7. These instructions

transfer data between the host/processor and the

DP7261; either between t he host and one of the data

registers or directly between the host and the Wiper

Control Register. These instructions are:

— XFR Data Register to Wiper Control Register

This transfers the contents of one specified Data

Register to the associated Wiper Control Register.

— XFR Wiper Control Register to Data Register

This transfers the contents of the specified Wiper

Control Register to the specified associated Data

Register.

— Global XFR Data Register to Wiper Control

Register

This transfers the contents of all specified Data

Registers

to

the

associated

Wiper

Control

Registers.

— Global XFR Wiper Counter Register to Data

Register

This transfers the contents of all Wiper Control

Registers

to

the

specified

associated

Data

Registers.

INCREMENT/DECREMENT COMMAND

The final command is Increment/Decrement (Figure 9

and 10). The Increment/Decrement command is differ-

ent from the other commands. Once the command is

issued the master can clock the selected wiper up

and/ or down in one segment steps; thereby providing

a fine tuning capability to the host. For each SCK

terminal. Similarly, for each SCK clock pulse while SI

is LOW, the selected wiper will move one resistor

See Instructions format for more detail.

Figure 8. Three-Byte Instruction Sequence

01

0

1

A2

A0

I2

I1

I0

R1 R0 P1

SI

ID3 ID2 ID1 ID0

P0

Device ID

Internal

Instruction

Opcode

Address

Register

Address

Pot/WCR

Address

A1

A3

I3

00

I3

I2

I1

I0

R1 R0

ID3 ID2 ID1 ID0

Device ID

Internal

Instruction

Opcode

Address

Data

Register

Address

Pot/WCR

Address

WCR[7:0]

or

Data Register D[7:0]

01

0

1

0

0

A2

A1

A0

P1 P0

SI

D7

D6 D5 D4 D3 D2

D1 D0

A3

I3

I2

I1

I0

ID3 ID2 ID1 ID0

Device ID

Internal

Instruction

Opcode

Address

Data

Register

Address

Pot/WCR

Address

010

1

00

A2

A1 A0

R0 P1 P0

SI

I

N

C

1

I

N

C

2

I

N

C

n

D

E

C

1

D

E

C

n

R1

A3