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ADT7461ARMZ-R7 数据表(PDF) 12 Page - ON Semiconductor

部件名 ADT7461ARMZ-R7
功能描述  Temperature Monitor with Series Resistance Cancellation
PDF  20 Pages
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制造商  ONSEMI [ON Semiconductor]
网页  http://www.onsemi.com
标志 ONSEMI - ON Semiconductor

ADT7461ARMZ-R7 数据表(HTML) 12 Page - ON Semiconductor

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ADT7461
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Table 13. LIST OF REGISTERS
Read Address (Hex)
Write Address (Hex)
Name
Power-On Default
Not Applicable
Not Applicable
Address Pointer
Undefined
0x00
Not Applicable
Local Temperature Value
0000 0000 (0x00)
0x01
Not Applicable
External Temperature Value High Byte
0000 0000 (0x00)
0x02
Not Applicable
Status
Undefined
0x03
0x09
Configuration
0000 0000 (0x00)
0x04
0x0A
Conversion Rate
0000 1000 (0x08)
0x05
0x0B
Local Temperature High Limit
0101 0101 (0x55) (85°C)
0x06
0x0C
Local Temperature Low Limit
0000 0000 (0x00) (0°C)
0x07
0x0D
External Temperature High Limit High Byte
0101 0101 (0x55) (85°C)
0x08
0x0E
External Temperature Low Limit High Byte
0000 0000 (0x00) (0°C)
Not Applicable
0x0F (Note 1)
One-Shot
0x10
Not Applicable
External Temperature Value Low Byte
0000 0000
0x11
0x11
External Temperature Offset High Byte
0000 0000
0x12
0x12
External Temperature Offset Low Byte
0000 0000
0x13
0x13
External Temperature High Limit Low Byte
0000 0000
0x14
0x14
External Temperature Low Limit Low Byte
0000 0000
0x19
0x19
External THERM Limit
0110 1100 (0x55) (85°C)
0x20
0x20
Local THERM Limit
0101 0101 (0x55) (85°C)
0x21
0x21
THERM Hysteresis
0000 1010 (0x0A) (10°C)
0x22
0x22
Consecutive ALERT
0000 0001 (0x01)
0xFE
Not Applicable
Manufacturer ID
0100 0001 (0x41)
0xFF
Not Applicable
Die Revision Code
0101 0001 (0x51)
1. Writing to Address ox0F causes the ADT7461 to perform a single measurement. It is not a data register, therefore, data written to it is
irrelevant.
Serial Bus Interface
Control of the ADT7461 is carried out via the serial bus.
The ADT7461 is connected to this bus as a slave device,
under the control of a master device.
After a conversion sequence completes, there should be
no SMBus transactions to the ADT7461 for at least one
conversion time, to allow the next conversion to complete.
The conversion time depends on the value programmed in
the conversion rate register.
The ADT7461 has an SMBus timeout feature. When this
is enabled, the SMBus times out typically after 25 ms of
inactivity. However, this feature is not enabled by default.
Bit 7 of the consecutive alert register (Address = 0x22)
should be set to enable it.
Consult the SMBus 1.1 specification for more
information (www.smbus.org).
Addressing the Device
In general, every SMBus device has a 7-bit device
address, except for some devices that have extended 10-bit
addresses. When the master device sends a device address
over the bus, the slave device with that address responds.
The ADT7461 is available with one device address, 0x4C
(1001 100b). The ADT7461-2 is also available with one
device address, 0x4D (1001 101b)
The serial bus protocol operates as follows:
1. The master initiates data transfer by establishing a
start condition, defined as a high-to-low transition
on the serial data line SDATA, while the serial
clock line SCLK remains high. This indicates that
an address/data stream will follow. All slave
peripherals connected to the serial bus respond to
the start condition and shift in the next eight bits,
consisting of a 7-bit address (MSB first) plus an
R/W bit, which determines the direction of the
data transfer, that is, whether data will be written
to or read from the slave device. The peripheral
whose address corresponds to the transmitted
address responds by pulling the data line low
during the low period before the ninth clock pulse,
known as the acknowledge bit. All other devices
on the bus now remain idle while the selected
device waits for data to be read from or written to
it. If the R/W bit is a 0, the master writes to the
slave device. If the R/W bit is a 1, the master reads
from the slave device.
2. Data is sent over the serial bus in a sequence of
nine clock pulses, eight bits of data followed by an
acknowledge bit from the slave device. Transitions
on the data line must occur during the low period



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