ADT7461

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13

of the clock signal and remain stable during the

high period, since a low-to-high transition when

the clock is high may be interpreted as a stop

signal. The number of data bytes that can be

transmitted over the serial bus in a single read or

write operation is limited only by what the master

and slave devices can handle.

3. When all data bytes have been read or written,

stop conditions are established. In write mode, the

master pulls the data line high during the tenth

clock pulse to assert a stop condition. In read

mode, the master device overrides the

acknowledge bit by pulling the data line high

during the low period before the ninth clock pulse.

This is known as a no acknowledge. The master

then takes the data line low during the low period

before the tenth clock pulse, then high during the

tenth clock pulse to assert a stop condition.

Any number of bytes of data may be transferred over the

serial bus in one operation, but it is not possible to mix read

and write in one operation because the type of operation is

determined at the beginning and cannot subsequently be

changed without starting a new operation. With the

ADT7461, write operations contain either one or two bytes,

while read operations contain one byte.

To write data to one of the device data registers or to read

data from it, the address pointer register must be set so that

the correct data register is addressed. The first byte of a write

operation always contains a valid address that is stored in the

address pointer register. If data is to be written to the device,

the write operation contains a second data byte that is written

to the register selected by the address pointer register.

This is illustrated in Figure 16. The device address is sent

over the bus followed by R/W set to 0. This is followed by two

data bytes. The first data byte is the address of the internal data

register to be written to, which is stored in the address pointer

register. The second data byte is the data to be written to the

internal data register. The examples shown in Figure 16 to

Figure 18 use the ADT7461 SMBus Address 0x4C.

Figure 16. Writing a Register Address to the Address Pointer Register, then Writing Data to the Selected Register

R/W

SCLK

SDATA

A2

A1

A0

D7

D6

D5

D4

D3

D2

D1

D0

ACK. BY

ADT7461

START BY

MASTER

19

1

ACK. BY

ADT7461

9

D7

D6

D5

D4

D3

D2

D1

D0

ACK. BY

ADT7461

STOP BY

MASTER

1

9

SCLK (CONTINUED)

SDATA (CONTINUED)

FRAME 1

SERIAL BUS ADDRESS BYTE

FRAME 2

ADDRESS POINTER REGISTER BYTE

FRAME 3

DATA BYTE

A3

A4

A5

A6

Figure 17. Writing to the Address Pointer Register Only

SCLK

SDATA

A2

A1

A0

D7

D6

D5

D4

D3

D2

D1

D0

ACK. BY

ADT7461

START BY

MASTER

19

1

ACK. BY

ADT7461

9

STOP BY

MASTER

FRAME 1

SERIAL BUS ADDRESS BYTE

FRAME 2

ADDRESS POINTER REGISTER BYTE

R/W

A3

A4

A5

A6

Figure 18. Reading Data from a Previously Selected Register

SCLK

SDATA

D7

D6

D5

D4

D3

D2

D1

D0

NACK. BY

MASTER

START BY

MASTER

9

1

ACK. BY

ADT7461

9

STOP BY

MASTER

A2

A1

A0

1

FRAME 1

SERIAL BUS ADDRESS BYTE

FRAME 2

DATA BYTE FROM ADT7461

R/W

A3

A4

A5

A6