ADT7461ARMZ-R7 datasheet(4/20 Pages) ONSEMI

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ADT7461

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Table 5. ELECTRICAL CHARACTERISTICS (TA = −40°C to +120°C, VDD = 3.0 V to 5.5 V, unless otherwise noted).

Parameter

Conditions

Min

Typ

Max

Unit

Power Supply

Supply Voltage, VDD

3.0

3.30

5.5

Average Operating Supply Current, IDD

0.0625 Conversions/Sec Rate (Note 1)

Standby Mode, –40°C ≤ TA ≤ +85°C

Standby Mode, +85°C ≤ TA ≤ +120°C

−

170

5.5

215

Undervoltage Lockout Threshold

VDD input, disables ADC, rising edge

2.2

2.55

2.8

Power-On-Reset Threshold

1.0

−

2.5

Temperature-To-Digital Converter

Local Sensor Accuracy

−40°C ≤ TA ≤ +100°C, 3.0 V ≤ VDD ≤ 3.6 V

−

±1.0

±3.0

°C

Resolution

−

1.0

−

°C

Remote Diode Sensor Accuracy

+60°C ≤ TA ≤ +100°C,

−55°C ≤ TD (Note 2) ≤ +150°C, 3.0 V ≤ VDD ≤ 3.6 V

−40°C ≤ TA ≤ +120°C,

−55°C ≤ TD (Note 2) ≤ +150°C, 3.0 V ≤ VDD ≤ 5.5 V

−

±1.0

±3.0

°C

Resolution

−

0.25

−

°C

Remote Sensor Source Current

High Level (Note 3)

Middle Level (Note 3)

Low Level (Note 3)

−

6.0

−

Conversion Time

From stop bit to conversion complete (both channels),

one-shot mode with averaging switched on

One-shot mode with averaging off (that is, conversion

rate = 16, 32, or 64 conversions per second)

32.13

3.2

−

114.6

12.56

Maximum Series Resistance Cancelled

Resistance split evenly on both the D+ and D– inputs

−

3.0

−

Open-Drain Digital Outputs (THERM, ALERT/THERM2)

Output Low Voltage, VOL

IOUT = −6.0 mA (Note 3)

−

0.4

High Level Output Leakage Current, IOH

VOUT = VDD (Note 3)

−

0.1

1.0

ALERT Output Low Sink Current

ALERT Forced to 0.4 V

1.0

−

SMBus Interface (Note 3 and 4)

Logic Input High Voltage, VIH SCLK, SDATA

3.0 V ≤ VDD ≤ 3.6 V

2.1

−

Logic Input Low Voltage, VIL SCLK, SDATA

3.0 V ≤ VDD ≤ 3.6 V

−

0.8

Hysteresis

−

500

−

SMBus Output Low Sink Current

SDATA Forced to 0.6 V

6.0

−

Logic Input Current, IIH, IIL

−1.0

−

+1.0

SMBus Input Capacitance, SCLK, SDATA

−

5.0

−

SMBus Clock Frequency

−

400

kHz

SMBus Timeout (Note 5)

User Programmable

−

SCLK Falling Edge to SDATA Valid Time

Master Clocking in Data

−

1.0

1. See Table 9 for information on other conversion rates.

2. Guaranteed by characterization, but not production tested.

3. Guaranteed by design, but not production tested.

4. See the SMBUS Timing Specifications section for more information.

5. Disabled by default; see the Serial Bus Interface section for details on enabling it.

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