SN65MLVD080

SN65MLVD082

SLLS581A − SEPTEMBER 2003 − REVISED SEPTEMBER 2003

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9

A

B

0 V or VCC

1.62 k

Ω , ±1%

VA or VB

Figure 7. Maximum Steady State Output Voltage

tc(n)

1/f0

0 V

0 V

Period Jitter

0 V

Peak to Peak Jitter

1/f0

PRBS INPUT

OUTPUT

VA −VB

VA −VB

CLOCK

INPUT

IDEAL

OUTPUT

ACTUAL

OUTPUT

VCC

VCC/2

tjit(per) =tc(n) −1/f0

tjit(pp)

0 V

VCC

VCC/2

0 V

VA −VB

VA −VB

Cycle to Cycle Jitter

0 V

VA − VB

OUTPUT

tc(n)

tc(n+1)

tjit(cc) = | tc(n) − tc(n+1) |

NOTES:A. All input pulses are supplied by an Agilent 8304A Stimulus System with plug-in TBD.

B. The measurement is made on a TEK TDS6604 running TDSJIT3 application software

C. Period jitter and cycle-to-cycle jitter are measured using a 100 MHz 50

±1% duty cycle clock input.

D. Peak-to-peak jitter and deterministic jitter are measured using a 200 Mbps 215−1 PRBS input.

Figure 8. Driver Jitter Measurement Waveforms

(VA + VB)/2

IO

R

VCM

VO

VID

VA

IA

A

B

IB

VB

Figure 9. Receiver Voltage and Current Definitions