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SN65MLVD080 数据表(PDF) 3 Page - Texas Instruments

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部件名 SN65MLVD080
功能描述  8 CHANNEL HALF DUPLEX M LVDS LINE TRANSCEIVERS
PDF  24 Pages
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制造商  TI [Texas Instruments]
网页  http://www.ti.com
标志 TI - Texas Instruments

SN65MLVD080 数据表(HTML) 3 Page - Texas Instruments

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SN65MLVD080
SN65MLVD082
SLLS581A − SEPTEMBER 2003 − REVISED SEPTEMBER 2003
www.ti.com
3
RECOMMENDED OPERATING CONDITIONS
MIN
NOM
MAX
UNIT
Supply voltage, VCC
3
3.3
3.6
V
High-level input voltage, VIH
2
VCC
V
Low-level input voltage, VIL
GND
0.8
V
Voltage at any bus terminal VA or VB
−1.4
3.8
V
Magnitude of differential input voltage,
VID
0.05
VCC
V
Operating free-air temperature, TA
−40
85
°C
Maximum junction temperature
140
°C
DEVICE ELECTRICAL CHARACTERISTICS
over recommended operating conditions unless otherwise noted
PARAMETER
TEST CONDITIONS
MIN
TYP(1)
MAX
UNIT
Driver only
RE and DE at VCC, RL = 50 Ω, All others open
110
140
Both disabled
RE at VCC, DE at 0 V, RL = No Load, All others open
5
8
ICC
Supply current
Both enabled
RE at 0 V, DE at VCC, RL = 50 Ω, CL = 15 pF, All others
open
140
180
mA
Receiver only
RE at 0 V, DE at 0 V, CL = 15 pF, All others open
38
50
(1) All typical values are at 25°C and with a 3.3-V supply voltage.
DRIVER ELECTRICAL CHARACTERISTICS
over recommended operating conditions unless otherwise noted
PARAMETER
TEST CONDITIONS
MIN(1)
TYP(2)
MAX
UNIT
VAB
Differential output voltage magnitude (A, B)
480
650
mV
∆VAB
Change in differential output voltage magnitude
between logic states (A, B)
See Figure 2
−50
50
mV
VOS(SS)
Steady-state common-mode output voltage (A, B)
0.8
1.2
V
VOS(SS)
Change in steady-state common-mode output
voltage between logic states (A, B)
See Figure 3
−50
50
mV
VOS(PP)
Peak-to-peak common-mode output voltage (A, B)
150
mV
VA(OC)
Maximum steady-state open-circuit output voltage
(A, B)
See Figure 7
0
2.4
V
VB(OC)
Maximum steady-state open-circuit output voltage
(A, B)
See Figure 7
0
2.4
V
VP(H)
Voltage overshoot, low-to-high level output (A, B)
See Figure 5
1.2 VSS
V
VP(L)
Voltage overshoot, high-to-low level output (A, B)
See Figure 5
−0.2 VSS
V
IIH
High-level input current (D, DE)
VIH = 2 V to VCC
10
µA
IIL
Low-level input current (D, DE)
VIL = GND to 0.8 V
10
µA
IOS
Differential short-circuit output current magnitude
(A, B)
See Figure 4
24
mA
Ci
Input capacitance (D, DE)
VI = 0.4 sin(30E6πt) + 0.5 V, (3)
5
pF
(1) The algebraic convention, in which the least positive (most negative) limit is designated as minimum is used in this data sheet.
(2) All typical values are at 25°C and with a 3.3-V supply voltage.
(3) HP4194A impedance analyzer (or equivalent)



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