SN65MLVD080

SN65MLVD082

SLLS581A − SEPTEMBER 2003 − REVISED SEPTEMBER 2003

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The maximum SSSC frequencies in a transparent mode can be calculated with the following equation:

Setup time and hold time on the receiver side are decided by the data processing unit, FPGA, or ASIC in this

example. By considering data passes through the transceiver only, the general calculation result is 238 MHz

when using the following data:

Output skew of data processing unit; any skew between data bits, or clock

and data bits

Driver part-to-part skew of the SN65MLVD082

Skew of propagation delay on the backplane between data and clock

Receiver part-to-part skew of the SN65MLVD082

The 238-MHz maximum operating speed calculated above was determined based on data and clock skews

only. Another important consideration when calculating the maximum operating speed is output transition time.

Transition-time-limited operating speed can be calculated from the following formula:

f

+ 45%

1

2

t

transition

Using the typical transition time of the SN65MLVD082 of 1.4 ns, a transition-time-limited operating frequency

of 170 MHz can be supported.

In addition to the high operating frequencies of SSSC that can be ensured, the SN65MLVD082 presents other

benefits as other M-LVDS bus transceivers can provide:

In dense backplane design, these benefits are important for improving the performance of the whole system.

A similar result can be achieved with the SN65MLVD080.