SN65MLVD080

SN65MLVD082

SLLS581A − SEPTEMBER 2003 − REVISED SEPTEMBER 2003

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2

These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during

storage or handling to prevent electrostatic damage to the MOS gates.

ORDERING INFORMATION

PART NUMBER

RECEIVER TYPE

PACKAGE MARKING

PACKAGE/CARRIER

SN65MLVD080DGG

Type 1

MLVD080

64-Pin TSSOP/Tube

SM65MLVD080DGGR

Type 1

MLVD080

64-Pin TSSOP/Tape and Reeled

SN65MLVD082DGG

Type 2

MLVD082

64-Pin TSSOP/Tube

SM65MLVD082DGGR

Type 2

MLVD082

64-Pin TSSOP/Tape and Reeled

PACKAGE DISSIPATION RATINGS

PACKAGE

PCB JEDEC

STANDARD

TA ≤ 25°C

POWER RATING

DERATING FACTOR(1)

ABOVE TA = 25°C

TA = 85°C

POWER RATING

DGG

Low-K(2)

1204.7 mW

10.5 mW/

_C

576 mW

DGG

High-K(3)

1839.4 mW

16.0 mW/

_C

880 mw

(1) This is the inverse of the junction-to-ambient thermal resistance when board mounted and with no air flow.

(2) In accordance with the Low-K thermal metric definitions of EIA/JESD51-3.

(3) In accordance with the High-K thermal metric definitions of EIA/JESD51-7.

THERMAL CHARACTERISTICS

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

Junction-to-board thermal resistance,

ΘJB

41.08

°C/W

Junction-to-case thermal resistance,

ΘJC

6.78

°C/W

VCC = 3.3 V, DE = VCC, RE = GND, CL = 15 pF,

RL = 50 Ω, 250 Mbps random data on each input

477

Device power dissipation

VCC = 3.6 V, DE = VCC, RE = GND, CL = 15 pF,

RL = 50 Ω, 250 Mbps data on one input and 125

MHz clock on the others

854(1)

mW

(1) When all channels are running at a 125-MHz clock frequency, a 250 lfm is required for a low-K board, and 150 lfm is required for a high-K board.

In such applications, a TI 1:8 or dual 1:4 M-LVDS buffer is highly recommended, SN65MLVD128 or SN65MLVD129, to fan out clock signals in

multiple paths.

ABSOLUTE MAXIMUM RATINGS

over operating free-air temperature range unless otherwise noted(1)

SN65MLVD080, 082

Supply voltage range(2), VCC

−0.5 V to 4 V

Input voltage range

D, DE, RE

−0.5 V to 4 V

Input voltage range

A, B

−1.8 V to 4 V

Output voltage range

R

−0.3 V to 4 V

Output voltage range

A, or B

−1.8 V to 4 V

Human Body Model(3)

A, B

±8 kV

Electrostatic discharge

Human Body Model(3)

All pins

±2 kV

Electrostatic discharge

Charged-Device Model(4)

All pins

±1500 V

Continuous power dissipation

See Dissipation Rating Table

Storage temperature range

−65

°C to 150°C

(1) Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and

functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not

implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

(2) All voltage values, except differential I/O bus voltages, are with respect to network ground terminal.

(3) Tested in accordance with JEDEC Standard 22, Test Method A114−A.

(4) Tested in accordance with JEDEC Standard 22, Test Method C101.