REV. 0

ADP3204

–7–

PIN FUNCTION DESCRIPTIONS (continued)

Pin

Mnemonic

Function

11

CLAMP

Clamp (Active High). This is open-drain output pin, via the assistance of an external pull-up

resistor, indicates that the core voltage should be clamped for its protection. To allow the highest

level of protection, the CLAMP signal is developed using both a redundant reference and a redun-

dant feedback path with respect to those of the main regulation loop. In a preferred and more

conservative configuration, the core voltage is clamped by an external FET. The initial protection

function is served when it is activated by detection of either an overvoltage or a reverse-voltage

condition on the COREFB pin. Due to loss of the latched signal at IC power-off, a backup protec-

tion function is served by connecting the pull-up resistor to a system “ALWAYS” regulator output

(e.g., V5_ALWAYS). If the external FET is used, this implementation will keep the core voltage

clamped until the ADP3204 has power reapplied, thus keeping protection for the CPU even after a

hard-failure power-down and restart (e.g., a shorted top or bottom FET).

12

DRVLSD

Drive-Low Shutdown (Active Low). In its active state, this digital output pin indicates that the

lower FET of the core VR should be disabled. In the suggested application schematic, this pin is

directly connected to the pin of the same name on the ADP3415 or other driver IC. Drive-low

shutdown is normally activated by the DPRSLP signal corresponding to a light load condition, but a

number of dynamic conditions can override the control of this pin as needed.

13

SS

Soft Start. The output of this analog I/O pin is a controlled current source used to charge or

discharge an external grounded capacitor; the input is the detected voltage that is indicative of

elapsed time. The pin controls the soft start time of the IC as well as the hiccup cycle time during

overload, including but not limited to short circuit. Hiccup operation was added to reduce short

circuit power dissipation by more than an order of magnitude, while still allowing an automatic

restart when the failure mode ceased. The hiccup operation can be overwritten and changed to

latched-off operation by clamping the SS pin voltage to a voltage level somewhere above ~ 0.2 V.

In this configuration, the controller does not restart after a hiccup cycle is initiated, but stays latched off.

14

COREFB

Core Feedback. This high impedance analog input pin is used to monitor the output voltage for

setting the proper state of the PWRGD and CLAMP pins. It is generally recommended to RC-filter

the noise from the monitored core voltage, as suggested by the application schematic.

15

DACRAMP

DAC Output Ramp Rate Setting. The rate at which the DAC output voltage can ramp up or down

from one voltage to another when the VID code changes can be controlled by an external

DACRAMP capacitor connected from this pin to the DACOUT pin. The time constant of the

DACOUT voltage variation is determined by the internal resistance appearing across the

DACRAMP and DACOUT pins, and the capacitance of the DACRAMP capacitor. Not having any

DACRAMP capacitor connected to these pins results in the fastest rate. Use of the DACRAMP rate

control and the Deeper Sleep Shift adjustment features are exclusive.

16

DACOUT

Digital-to-Analog Converter Output of the VID input. This output voltage is the VID controlled

reference voltage whose primary function is to determine the output voltage regulation point.

17

GND

Ground

18–20

OUT1–3

Outputs to Driver 1–3. These digital output pins are used to command the state of theswitched

nodes via the drivers. They should be connected to the IN pin of the drivers of the appropriate channels.

21

CS1

Current Sense, Channel 1. This high impedance analog input pin is used for providing negative

feedback of the current information for the first channel.

22

CS2

Current Sense, Channel 2. This high impedance analog input pin is used to provide negative

feedback of the current information for the second channel. The pin is also used to determine

whether the chip is acting as a single or a multiphase controller. If the CS2 pin is tied to VCC but

not to a sense resistor, then three-phase operation is disabled. In this condition, the second phase

output signal (OUT2) is not switching but stays static low; the first and third phase output signals

(OUT1 and OUT2) are switching in phase. It’s the user’s discretion to use only one or both of the

two signals to drive a single- or dual-channel power stage.

23

CS3

Current Sense, Channel 3. This high impedance analog input pin is used to provide negative

feedback of the current information for the third channel. The pin is also used to determine

whether the chip is acting as a dual- or three-phase controller. If the pin is tied to VCC but not to a

sense resistor, then three-phase operation is disabled; the chip works as a dual-phase controller. In

this condition, the third phase output signal (OUT3) is not switching but stays static low; the first

and second phase output signals (OUT1, OUT2) are interleaved out-of-phase signals. In single-

phase operation, CS3 should be left open instead of being tied to VCC.