REV. 0

–8–

ADP3204

PIN FUNCTION DESCRIPTIONS (continued)

Pin

Mnemonic

Function

24

VCC

Power Supply. This should be connected to the system’s 3.3 V power supply output.

25

RAMP

Regulation Ramp Feedback Input. The RAMP pin voltage is compared against the REG pin for

cycle-by-cycle switching response. Several switched current sources also appear at this input: the

cycle-by-cycle hysteresis-setting switched current programmed by the HYSSET pin, the

BOM shift

current programmed by the BSHIFT pin, and the Deep Sleep shift current programmed by the

DSHIFT pin. The external resistive termination at this pin sets the magnitude of the hysteresis

applied to the regulation loop.

26

REG

Regulation Voltage Summing Input. This is a high impedance analog input pin into which the

voltage reference of the feedback loop allows the summing of both the DACOUT voltage and the

core voltage for programming the output resistance of the core voltage regulator. This is also the pin

at which an optimized transient response can be tailored using Analog Devices’ patented ADOPT

design technique.

27

CS+

Current Limit Positive Sense. This high impedance analog I/O pin is multiplexed between either of

the three current-sense inputs during the high state of the OUT pin of the respective channel.

During the common off-time of both channels, the pin voltage reflects the average of the three

channels. The multiplexed current sense signal is passed to the core comparator through an external

resistive termination connected from this pin to the RAMP pin. The external (RAMP) resistor sets

the magnitude of the hysteresis applied to the regulation loop.

28

CS–

Current Limit Negative Sense. This high impedance analog input pin which is normally Kelvin

connected to the negative node of the current sense resistor(s) via a current-limit programming

resistor. A hysteretically-controlled current—three times the current programmed at the HYSSET

pin—also flows out of this pin and develops a current-limit-setting voltage across that resistor, which

must then be matched by the inductor current flowing in the current sensing resistor in order to

trigger the current limit function. When triggered, the current flowing out of this pin is reduced to

two-thirds of its previous value, producing hysteresis in the current limiting function.

29

HYSSET

Hysteresis Set. This is an analog I/O pin whose output is the VID reference voltage and whose input

is a current that is programmed by an external resistance to ground. The current is used in the IC to

set the hysteretic currents for the Core Comparator and the Current Limit Comparator. Modifica-

tion of the resistance will affect both the hysteresis of the feedback regulation, and the current limit

set point and hysteresis.

30

DSHIFT

Deep Sleep Shift. This is an analog I/O pin whose output is the VID reference voltage and whose

input is a current that is programmed by an external resistance to ground. The current is used in the

IC to set a switched bias current out of the RAMP pin, depending on whether it is activated by the

DSLP signal. When activated, this added bias current creates a downward shift of the regulated core

voltage to a predetermined optimum level for regulation corresponding to Deep Sleep Mode of

CPU operation. The use of the DACOUT voltage as the reference makes the Deep Sleep offset a

fixed percentage of the VID setting, as required by specifications.

31

BSHIFT

Battery Optimized Mode (

BOM) Shift. This is an analog I/O pin whose output is the VID reference

voltage and whose input current is programmed by an external resistance to ground. The current is

used in the IC to set a switched bias current out of the RAMP pin, depending on whether it is

activated by the

BOM signal. When activated, this added bias current creates a downward shift

of the regulated core voltage to a predetermined optimum level for regulation corresponding to

Battery Optimized Mode of CPU operation. The use of the DACOUT voltage as the reference

makes the DSHIFT a fixed percentage of the VID setting, as required by specifications.