ADP5071ACPZ-R7 datasheet(6/28 Pages) AD

6 / 28 page

Data Sheet

ADP5071

Rev. A | Page 5 of 27

ABSOLUTE MAXIMUM RATINGS

Table 3.

Parameter

Rating

PVIN1, PVIN2, PVINSYS

−0.3 V to +18 V

INBK

−0.3 V to PVIN1 + 0.3 V

SW1

−0.3 V to +40 V

SW2

PVIN2 − 40 V to PVIN2 + 0.3 V

PGND, AGND

−0.3 V to +0.3 V

VREG

−0.3 V to lower of PVINSYS +

0.3 V or +6 V

EN1, EN2, FB1, FB2, SYNC/FREQ

−0.3 V to +6 V

COMP1, COMP2, SLEW, SS,

SEQ, VREF

−0.3 V to VREG + 0.3 V

Operating Junction

Temperature Range

−40°C to +125°C

Storage Temperature Range

−65°C to +150°C

Soldering Conditions

JEDEC J-STD-020

Stresses at or above those listed under Absolute Maximum

Ratings may cause permanent damage to the product. This is a

stress rating only; functional operation of the product at these

or any other conditions above those indicated in the operational

section of this specification is not implied. Operation beyond

the maximum operating conditions for extended periods may

affect product reliability.

THERMAL RESISTANCE

θJA and ΨJT are based on a 4-layer printed circuit board (PCB)

(two signal and two power planes) with nine thermal vias

connecting the exposed pad to the ground plane as recommended

in the Layout Considerations section. θJC is measured at the top

of the package and is independent of the PCB. The ΨJT value is

more appropriate for calculating junction to case temperature in

the application.

Table 4. Thermal Resistance

Package Type

θJA

θJC

ΨJT

Unit

20-Lead LFCSP

60.2

36.5

0.63

°C/W

20-Lead TSSOP

58.5

35.0

0.60

°C/W

ESD CAUTION

ADP5071ACPZ-R7 数据表(PDF) 6 Page - Analog Devices

ADP5071ACPZ-R7 数据表(HTML) 6 Page - Analog Devices

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28

数据表下载