ADP5071

Data Sheet

Rev. A | Page 6 of 27

PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS

14

13

12

1

3

4

VREG

15 PVIN1

AGND

VREF

11 FB2

INBK

SEQ

2

SYNC/FREQ

SLEW

5

FB1

ADP5071

TOP VIEW

(Not to Scale)

NOTES

1. EXPOSED PAD. CONNECT THE EXPOSED PAD TO AGND.

Figure 2. 20-Lead LFCSP Pin Configuration

1

2

3

4

5

6

7

8

9

10

20

19

18

17

16

15

14

13

12

11

SW1

INBK

SYNC/FREQ

FB1

SLEW

SEQ

PGND

PVIN2

PVINSYS

PVIN1

VREF

AGND

VREG

SS

EN1

COMP1

EN2

COMP2

FB2

SW2

ADP5071

TOP VIEW

NOTES

1. EXPOSED PAD. CONNECT THE EXPOSED PAD TO AGND.

Figure 3. 20-Lead TSSOP Pin Configuration

Table 5. Pin Function Descriptions

Pin No.

Mnemonic

Description

LFCSP

TSSOP

1

3

INBK

Input Disconnect Switch Output for the Boost Regulator.

2

4

SYNC/FREQ

Frequency Setting and Synchronization Input. To set the switching frequency to 2.4 MHz, pull the SYNC/FREQ

pin high. To set the switching frequency to 1.2 MHz, pull the SYNC/FREQ pin low. To synchronize the

switching frequency, connect the SYNC/FREQ pin to an external clock.

3

5

SEQ

(the EN1 pin can be used to enable the internal references early, if required). For a sequenced startup, pull the

SEQ pin low. Either EN1 or EN2 can be used, and the corresponding supply is the first in sequence; hold

the other enable pin low.

4

6

SLEW

Driver Stage Slew Rate Control. The SLEW pin sets the slew rate for the SW1 and SW2 drivers. For the

fastest slew rate (best efficiency), leave the SLEW pin open. For normal slew rate, connect the SLEW pin to

VREG. For the slowest slew rate (best noise performance), connect the SLEW pin to AGND.

5

7

FB1

Feedback Input for the Boost Regulator. Connect a resistor divider between the positive side of the boost

regulator output capacitor and AGND to program the output voltage.

6

8

COMP1

Error Amplifier Compensation for the Boost Regulator. Connect the compensation network between this

pin and AGND.

7

9

EN1

Boost Regulator Precision Enable. The EN1 pin is compared to an internal precision reference to enable

the boost regulator output.

8

10

SS

Soft Start Programming. Leave the SS pin open to obtain the fastest soft start time. To program a slower

soft start time, connect a resistor between the SS pin and AGND.

9

11

EN2

Inverting Regulator Precision Enable. The EN2 pin is compared to an internal precision reference to enable

the inverting regulator output.

10

12

COMP2

Error Amplifier Compensation for the Inverting Regulator. Connect the compensation network between

this pin and AGND.

11

13

FB2

Feedback Input for the Inverting Regulator. Connect a resistor divider between the negative side of the

inverting regulator output capacitor and VREF to program the output voltage.

12

14

VREF

Inverting Regulator Reference Output. Connect a 1.0 μF ceramic filter capacitor between the VREF pin and

AGND.

13

15

AGND

Analog Ground.

14

16

VREG

Internal Regulator Output. Connect a 1.0 μF ceramic filter capacitor between the VREG pin and AGND.

15

17

PVIN1

Power Input for the Boost Regulator.

16

18

PVINSYS

System Power Supply for the ADP5071.

17

19

PVIN2

Power Input for the Inverting Regulator.