ADP5071ACPZ-R7 datasheet(16/28 Pages) AD

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Data Sheet

ADP5071

Rev. A | Page 15 of 27

PRECISION ENABLING

The ADP5071 has an individual enable pin for the boost and

inverting regulators: EN1 and EN2. The enable pins feature a

precision enable circuit with an accurate reference voltage. This

reference allows the ADP5071 to be sequenced easily from other

supplies. It can also be used as a programmable UVLO input by

using a resistor divider.

The enable pins have an internal pull-down resistor that defaults

each regulator to off when the pin is floating.

When the voltage at the enable pins is greater than the VTH_H

reference level, the regulator is enabled.

SOFT START

Each regulator in the ADP5071 includes soft start circuitry that

ramps the output voltage in a controlled manner during startup,

thereby limiting the inrush current. The soft start time is internally

set to the fastest rate when the SS pin is open.

Connecting a resistor between SS and AGND allows the adjust-

ment of the soft start delay. The delay length is common to both

regulators.

SLEW RATE CONTROL

The ADP5071 employs programmable output driver slew rate

control circuitry. This circuitry reduces the slew rate of the

switching node as shown in Figure 41, resulting in reduced

ringing and lower EMI. To program the slew rate, connect the

SLEW pin to the VREG pin for normal mode, to the AGND pin

for slow mode, or leave it open for fast mode. This configuration

allows the use of an open-drain output from a noise sensitive

device to switch the slew rate from fast to slow, for example,

during analog-to-digital converter (ADC) sampling.

Note that slew rate control causes a trade-off between efficiency

and low EMI.

FASTEST

SLOWEST

Figure 41. Switching Node at Various Slew Rate Settings

CURRENT-LIMIT PROTECTION

The boost and inverting regulators in the ADP5071 include

current-limit protection circuitry to limit the amount of forward

current through the MOSFET switch.

When the peak inductor current exceeds the overcurrent limit

threshold for a number of clock cycles during an overload or

short-circuit condition, the regulator enters hiccup mode. The

regulator stops switching and then restarts with a new soft start

cycle after tHICCUP and repeats until the overcurrent condition is

removed.

OVERVOLTAGE PROTECTION

An overvoltage protection mechanism is present on the FB1

and FB2 pins for the boost and inverting regulators.

On the boost regulator, when the voltage on the FB1 pin exceeds

the VOV1 threshold, the switching on SW1 stops until the voltage

falls below the threshold again. This functionality is permanently

enabled on this regulator.

On the inverting regulator, when the voltage on the FB2 pin

drops below the VOV2 threshold, the switching stops until the

voltage rises above the threshold. This functionality is enabled

after the soft start period has elapsed.

THERMAL SHUTDOWN

In the event that the ADP5071 junction temperature rises above

TSHDN, the thermal shutdown circuit turns off the IC. Extreme

junction temperatures can be the result of prolonged high current

operation, poor circuit board design, and/or high ambient temper-

ature. Hysteresis is included so that when thermal shutdown occurs,

the ADP5071 does not return to operation until the on-chip

temperature drops below TSHDN minus THYS. When resuming from

thermal shutdown, a soft start is performed on each enabled

channel.

START-UP SEQUENCE

The ADP5071 implements a flexible start-up sequence to meet

different system requirements. Three different enabling modes

can be implemented via the SEQ pin, as explained in Table 7.

Table 7. SEQ Pin Settings

SEQ Pin

Description

Open

Manual enable mode

VREG

Simultaneous enable mode

Low

Sequential enable mode

To configure the manual enable mode, leave the SEQ pin open.

The boost and inverting regulators are controlled separately from

their respective precision enable pins.

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