MT9072AB datasheet(122/275 Pages) ZARLINK

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MT9072

Data Sheet

122

Zarlink Semiconductor Inc.

Bit

Name

Functional Description

15-12

not used.

11-7

HCH4-0

(0)

HDLC Channel 4-0. This 5 bit number specifies the timeslot the HDLC will be attached to if

enabled. Timeslot 0 is the first channel in the frame. Timeslot 23 is the last channel available

in a T1 frame. If enabled in a channel, HDLC data will be substituted for data from DSTi on

the transmit side. Receive data is extracted from the incoming line data before the elastic

buffer.

HPAYSEL

(0)

HDLC Payload Select. Set this bit to 1 to attach HDLC to a payload timeslot, if zero it is

attached to the Facility Data Link when in the ESF mode.

E1.5CK

(0)

Extracted 1.5 Data Link Clock. If one, the RxDLC pin outputs a 1.544 MHz clock signal

derived from the 1.544 MHz clock signal at the EXCLi pin. This clock is synchronous with the

receive data before it passes through the elastic buffer at the RxDL pin. If zero, the RxDLC

pin operates as a receive data link clock or enable signal as programmed by control bit

DLCK (register address Y06).

4DLCK

(0)

Data Link Clock. If one, the TxDLC and RxDLC pins output a gapped clock. If zero, the

TxDLC and RxDLC pins output an active low enable signal.

3EDLEN

(0)

Enable Data Link. Setting this bit multiplexes the serial stream clocked in on pin TxDL into

the FDL bit position (ESF mode) or the Fs bit position (D4 mode).

BOMEN

(0)

Bit Oriented Message Enable. Setting this bit enables transmission of bit - oriented

messages on the ESF facility data link. The actual message transmitted at any one time is

contained in the Tx BOM register (Y07).

HDLCEN

(0)

HDLC Enable. If this bit is set and HPAYSEL is a zero than the internal HDLC is connected

to the FDL bits in ESF Mode and TXDL/RXDL are not used for the dataLink. If 0 the datalink

is sourced/sinked from TXDL/RXDL.

H1R64

(0)

HDLC Rate Select. Setting this bit high while the HDLC is activated on a timeslot enables

64 Kb/s operation. Setting this bit low while an HDLC is activated enables 56 Kb/s operation

(this prevents data corruption due to forced bit stuffing).

Table 69 - HDLC & DataLink Control Word(Y06) (T1)

Bit

Name

Functional Description

15-8

not used.

7-0 TXBOM

7-0

(0)

Transmit Bit Oriented Message. The contents of this register are concatenated with a

sequence of eight 1’s and continuously transmit in the FDL bit position of ESF trunks. Normally

the leading bit (bit 7) and last bit (bit 0) of this register are set to zero. Note that in accordance to

T1.403 Table 11 the codeword 7E should not be used due to similarity of DataLink idle code.

Table 70 - Transmit Bit Oriented Message Register (Y07) (T1)

MT9072AB 数据表(PDF) 122 Page - Zarlink Semiconductor Inc

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