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ADM1034 数据表(PDF) 22 Page - Analog Devices

部件名 ADM1034
功能描述  Thermal Monitor and Fan Speed (RPM) Controller
PDF  40 Pages
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制造商  AD [Analog Devices]
网页  http://www.analog.com
标志 AD - Analog Devices

ADM1034 数据表(HTML) 22 Page - Analog Devices

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ADM1034
Rev. 0 | Page 22 of 40
HANDLING SMBusALERT INTERRUPTS
TEMPERATURE
INTERRUPT MASK BIT
CLEARED
(SMBusALERT REARMED)
CLEARED ON READ
(TEMP BELOW LIMIT)
INTERRUPT
MASK BIT SET
HIGH LIMIT
SMBusALERT
"STICKY"
STATUS BIT
TEMP BACK IN LIMIT
(STATUS BIT STAYS SET)
Figure 32. Handling SMBusALERT
To prevent tie-ups due to service interrupts, follow these steps:
1.
Detect an SMBus assertion.
2.
Enter the interrupt handler.
3.
Read the status register to identify the interrupt source.
4.
Mask the interrupt source by setting the appropriate mask
bit in the interrupt mask registers (from Reg. 0x08 to
Reg. 0x0A).
5.
Take the appropriate action for a given interrupt source.
6.
Exit the interrupt handler.
7.
Periodically poll the status register. If the interrupt status
bit clears, reset the corresponding interrupt mask bit to 0.
The SMBusALERT output and status bits then behave as
shown in Figure 32.
INTERRUPT MASKING REGISTER
Mask Registers 1, 2, and 3 are located at Addresses 0x08, 0x09,
and 0x0A. These allow individual interrupt sources to be
masked out to prevent the SMBusALERT interrupts. Masking
the interrupt source prevents only the SMBusALERT from
being asserted; the appropriate status bit is still set as normal.
Table 19. Mask Register 1 (Reg. 0x08)
Bit No.
Name
Description
7
LH
1 masks the ALERT for the local high
temperature.
6
LL
1 masks the ALERT for the local low
temperature.
5
R1H
1 masks the ALERT for the Remote 1 high
temperature.
4
R1L
1 masks the ALERT for the Remote 1 low
temperature.
3
R1D
1 masks the ALERT for the Remote 1 diode
errors.
2
R2H
1 masks the ALERT for the Remote 2 high
temperature.
1
R2L
1 masks the ALERT for the Remote 2 low
temperature.
0
R2D
1 masks the ALERT for the Remote 2 diode
errors.
Table 20. Mask Register 2 (Reg. 0x09)
Bit No.
Name
Description
7
Res
Reserved.
6
Res
Reserved.
5
Res
Reserved.
4
T%
1 masks the ALERT for the THERM % ontime
limit.
3
TA
1 masks the ALERT for the THERM limit
being exceeded and the THERM output
signal being asserted.
2
TS
1 masks the ALERT for the THERM state; has
no effect on ALERT in ALERT comp mode.
1
Res
Reserved.
0
Res
Reserved.
Table 21. Mask Register 3 (Reg. 0x0A)
Bit No.
Name
Description
7
F1S
1 masks the ALERT for Fan 1 stalling.
6
FA
1 masks the ALERT for fans at ALARM speed.
5
F2S
1 masks the ALERT for Fan 2 stalling.
4
Res
Reserved.
3
Res
Reserved.
2
Res
Reserved.
1
Res
Reserved.
0
Res
Reserved.



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