ST72F321 datasheet(123/189 Pages) STMICROELECTRONICS

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ST72321

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I2C BUS INTERFACE (Cont’d)

I2C STATUS REGISTER 1 (SR1)

Read Only

Reset Value: 0000 0000 (00h)

Bit 7 = EVF Event flag.

This bit is set by hardware as soon as an event oc-

curs. It is cleared by software reading SR2 register

in case of error event or as described in Figure 67.

It is also cleared by hardware when the interface is

disabled (PE=0).

0: No event

1: One of the following events has occurred:

– BTF=1 (Byte received or transmitted)

– ADSL=1 (Address matched in Slave mode

while ACK=1)

– SB=1 (Start condition generated in Master

mode)

– AF=1 (No acknowledge received after byte

transmission)

– STOPF=1 (Stop condition detected in Slave

mode)

– ARLO=1 (Arbitration lost in Master mode)

– BERR=1 (Bus error, misplaced Start or Stop

condition detected)

– ADD10=1 (Master has sent header byte)

– Address byte successfully transmitted in Mas-

ter mode.

Bit 6 = ADD10 10-bit addressing in Master mode.

This bit is set by hardware when the master has

sent the first byte in 10-bit address mode. It is

cleared by software reading SR2 register followed

by a write in the DR register of the second address

byte. It is also cleared by hardware when the pe-

ripheral is disabled (PE=0).

0: No ADD10 event occurred.

1: Master has sent first address byte (header)

Bit 5 = TRA Transmitter/Receiver.

When BTF is set, TRA=1 if a data byte has been

transmitted. It is cleared automatically when BTF

is cleared. It is also cleared by hardware after de-

tection of Stop condition (STOPF=1), loss of bus

arbitration (ARLO=1) or when the interface is disa-

bled (PE=0).

0: Data byte received (if BTF=1)

1: Data byte transmitted

Bit 4 = BUSY Bus busy.

This bit is set by hardware on detection of a Start

condition and cleared by hardware on detection of

a Stop condition. It indicates a communication in

progress on the bus. The BUSY flag of the I2CSR1

0: No communication on the bus

1: Communication ongoing on the bus

Note:

– The BUSY flag is NOT updated when the inter-

face is disabled (PE=0). This can have conse-

quences when operating in Multimaster mode;

i.e. a second active I2C master commencing a

transfer with an unset BUSY bit can cause a con-

flict resulting in lost data. A software workaround

consists of checking that the I2C is not busy be-

fore enabling the I2C Multimaster cell.

Bit 3 = BTF Byte transfer finished.

This bit is set by hardware as soon as a byte is cor-

rectly received or transmitted with interrupt gener-

ation if ITE=1. It is cleared by software reading

SR1 register followed by a read or write of DR reg-

ister. It is also cleared by hardware when the inter-

face is disabled (PE=0).

– Following a byte transmission, this bit is set after

reception of the acknowledge clock pulse. In

case an address byte is sent, this bit is set only

after the EV6 event (See Figure 67). BTF is

cleared by reading SR1 register followed by writ-

ing the next byte in DR register.

– Following a byte reception, this bit is set after

transmission of the acknowledge clock pulse if

ACK=1. BTF is cleared by reading SR1 register

followed by reading the byte from DR register.

The SCL line is held low while BTF=1.

0: Byte transfer not done

1: Byte transfer succeeded

Bit 2 = ADSL Address matched (Slave mode).

This bit is set by hardware as soon as the received

slave address matched with the OAR register con-

tent or a general call is recognized. An interrupt is

generated if ITE=1. It is cleared by software read-

ing SR1 register or by hardware when the inter-

face is disabled (PE=0).

The SCL line is held low while ADSL=1.

0: Address mismatched or not received

1: Received address matched

EVF

ADD10

TRA

BUSY

BTF

ADSL

M/SL

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