ST72F321 datasheet(124/189 Pages) STMICROELECTRONICS

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ST72321

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I2C BUS INTERFACE (Cont’d)

Bit 1 = M/SL Master/Slave.

This bit is set by hardware as soon as the interface

is in Master mode (writing START=1). It is cleared

by hardware after detecting a Stop condition on

the bus or a loss of arbitration (ARLO=1). It is also

cleared when the interface is disabled (PE=0).

0: Slave mode

1: Master mode

Bit 0 = SB Start bit (Master mode).

This bit is set by hardware as soon as the Start

condition

generated

(following

write

START=1). An interrupt is generated if ITE=1. It is

cleared by software reading SR1 register followed

by writing the address byte in DR register. It is also

cleared by hardware when the interface is disa-

bled (PE=0).

0: No Start condition

1: Start condition generated

I2C STATUS REGISTER 2 (SR2)

Read Only

Reset Value: 0000 0000 (00h)

Bit 7:5 = Reserved. Forced to 0 by hardware.

Bit 4 = AF Acknowledge failure.

This bit is set by hardware when no acknowledge

is returned. An interrupt is generated if ITE=1. It is

cleared by software reading SR2 register or by

hardware when the interface is disabled (PE=0).

The SCL line is not held low while AF=1 but by oth-

er flags (SB or BTF) that are set at the same time.

0: No acknowledge failure

1: Acknowledge failure

Note:

– When an AF event occurs, the SCL line is not

held low; however, the SDA line can remain low

if the last bits transmitted are all 0. It is then nec-

essary to release both lines by software.

Bit 3 = STOPF Stop detection (Slave mode).

This bit is set by hardware when a Stop condition

is detected on the bus after an acknowledge (if

ACK=1). An interrupt is generated if ITE=1. It is

cleared by software reading SR2 register or by

hardware when the interface is disabled (PE=0).

The SCL line is not held low while STOPF=1.

0: No Stop condition detected

1: Stop condition detected

Bit 2 = ARLO Arbitration lost.

This bit is set by hardware when the interface los-

es the arbitration of the bus to another master. An

interrupt is generated if ITE=1. It is cleared by soft-

ware reading SR2 register or by hardware when

the interface is disabled (PE=0).

After an ARLO event the interface switches back

automatically to Slave mode (M/SL=0).

The SCL line is not held low while ARLO=1.

0: No arbitration lost detected

1: Arbitration lost detected

Note:

– In a Multimaster environment, when the interface

is configured in Master Receive mode it does not

perform arbitration during the reception of the

Acknowledge Bit. Mishandling of the ARLO bit

from the I2CSR2 register may occur when a sec-

ond master simultaneously requests the same

data from the same slave and the I2C master

does not acknowledge the data. The ARLO bit is

then left at 0 instead of being set.

Bit 1 = BERR Bus error.

This bit is set by hardware when the interface de-

tects a misplaced Start or Stop condition. An inter-

rupt is generated if ITE=1. It is cleared by software

reading SR2 register or by hardware when the in-

terface is disabled (PE=0).

The SCL line is not held low while BERR=1.

0: No misplaced Start or Stop condition

1: Misplaced Start or Stop condition

Note:

– If a Bus Error occurs, a Stop or a repeated Start

condition should be generated by the Master to

re-synchronize communication, get the transmis-

sion acknowledged and the bus released for fur-

ther communication

Bit 0 = GCAL General Call (Slave mode).

This bit is set by hardware when a general call ad-

dress is detected on the bus while ENGC=1. It is

cleared by hardware detecting a Stop condition

(STOPF=1) or when the interface is disabled

(PE=0).

0: No general call address detected on bus

1: general call address detected on bus

STOPF ARLO

BERR

GCAL

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