PC87310 datasheet(21/52 Pages) NSC

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40 Functional Description (Continued)

TLC10591 – 8

FIGURE 2 Block Diagram of the Data Separator

TLC10591 – 9

a) Single Data Rate

TLC10591 – 10

b) 250500 kbs Filter

TLC10591 – 11

c) 250500 kbs and 1 Mbs

Note

For all filter configurations 250 kbs and 300 kbs share the same filter

FIGURE 3 Typical Configuration for Loop Filters for the FDC Showing Component Labels

To ensure optimal performance the data separator incorpo-

rates several additional circuits The quarter period delay

line is used to determine the center of each bit cell A sec-

ondary PLL is used to automatically calibrate the quarter

period delay line The secondary PLL also calibrates the

center frequency of the VCO

To eliminate the logic associated with controlling multiple

data rates the floppy disk controller (FDC) supports the con-

nection of three filters to the chip via the FGND250 and

FGND500 pins (filter ground switches)

The controller

chooses which filter components to use based on the value

loaded in the Data Rate Register If 500 k(MFM) is being

used then the FGND500 is enabled (FGND250 is disabled)

If 250 k(MFM) or 300 k(MFM) is being used the FGND250

pin is enabled and FGND500 is disabled For 1 Mbs

(MFM) both FGND pins are disabled

Note for FM encoding

Sometimes after a reset the FDC will consistently

return an error in the Result Phase after an FM read command If this oc-

curs simply reset the FDC and retry the operation This may have to be

done more than once as many as five times Resetting and repeating will

prevent soft errors being reported prematurely This technique is used by

MS-DOS

Figure 3 shows several possible filter configurations For a

filter to cover all data rates

(Figure 3c) the FDC has a

1 Mbs filter always connected and other capacitor filter

components for the other data rates are switched in parallel

to this filter The actual loop filter for 500 kbs is the parallel

combination of the two capacitors C2C and C2B attached

to the FGND500 pin and to ground The 250300 kbs filter

is the parallel combination of the capacitors C2C and C2A

attached to the FGND250 and ground If 1 Mbs need not

be supported then the filter configuration of

Figure 3b can

be used This configuration allows more optimal perform-

ance for both 500k and 250300 kbs

Figure 3a is a simple

filter configuration primarily for a single data rate (or multiple

data rates with a performance compromise) Table 4-8

shows some typical filter values Other filter configurations

and values are possible these result in good general per-

formance

While the controller and data separator support both FM

and MFM encoding the filter switch circuitry only supports

the IBM standard MFM data rates To provide both FM and

MFM filters external logic may be necessary

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