PC87310 datasheet(13/52 Pages) NSC

13 / 52 page

40 Functional Description

This section provides the descriptions for each of the major

functional blocks of the PC87310 Each functional block is

described as independently of the other blocks as is possi-

ble Software can address all blocks independently of each

other except for the Configuration Port and low power

mode operation The Configuration Register affects all other

blocks by determining which ones the address decoder can

activate The low power mode is enabled and disabled via

the floppy disk controller mode command Enabling low

power mode will stop the 24 MHz crystal and clock oscilla-

tion to all logic blocks Software should ensure that both

UARTs and the floppy disk controller are idle and will con-

tinue to be idle while the low power mode is enabled

41 ADDRESS DECODER

This decodes address signals A0 – A9 qualifies them and if

they qualify it activates the appropriate function block The

XTSEL pin determines whether function blocks respond to

the industry standard XT or AT address

Before activating the block it qualifies the address with IOL

AEN and the Configuration Register enable signals for

each function If IOL is low (active) then an external decod-

er has determined that address bits A10 – A15 are all zero

and this is an IO access If AEN is low (active) then this is

a CPU (not DMA) access and the addressed register can

respond If the configuration bit for the addressed function is

0 that function is active on this particular device and can

respond

There are no pin selects for the functions on this device so

the designer must use the on-chip address decoder to se-

lect any function Each function except for the hard disk

select can be disabled via hardware or software The hard

disk select can only be disabled via software

42 CONFIGURATION PORT

This port consists of a one byte register that the system can

program via hardware (voltage levels on certain pins during

reset) or software (two consecutive writes to IO address

03f3 hex) When programming the Configuration Register

via software the data sent during both writes to 03f3 hex

should be the correct bit pattern and there should be no IO

write strobes between these 03f3 hex accesses Further-

more system interrupts should be disabled to prevent inter-

rupt service routines from issuing IO write strobes between

the 03f3 hex accesses Through this register the system

can enable disable or reassign addresses to the on-chip

functions

One pin (CRPE) determines whether the default value of

this register will be 00 (all functions enabled) or a value

latched in during reset from the CRBx pins If CRPE is low

during reset the complement of the CRBx pins will be load-

ed into the bits of the Configuration Register

Bit 5 Hard Drive Chip Select does not have an external pin

associated with it and will always default to the enabled

state If CRPE is high during reset then 00 will be loaded

into the Configuration Register After reset the value of this

of CRPE

The Configuration Register bits are defined in Table 4-1 An

example of the initial condition after reset if 00 is loaded into

the Configuration Register is

1 The parallel port responds to address range 378 – 37A

(LPT2)

2 Serial Port 1 responds to 3F8 – 3FF (COM1)

3 Serial Port 2 responds to 2F8 – 2FF (COM2)

4 The hard disk selects are enabled

5 The floppy disk controller is enabled

6 The floppy disk controller drive and motor pins can drive

the disk interface directly (no encoded information is pre-

sented)

TABLE 4-1 Configuration Register Bit Definitions

Result

Parallel port at LPT2 (378 – 37F)

Parallel port at LPT1 (3BC – 3BE)

Parallel port at LPT3 (278 – 27F)

Parallel port disabled

UART1

UART2

COM1 (3F8 – 3FF)

COM2 (2F8 – 2FF)

disabled

COM2

COM1

disabled

COM2

COM1

disabled

COM1

COM2

disabled

Hard disk select enabled

Hard disk select disabled

Floppy disk controller enabled

Floppy disk controller disabled

DR0 DR1 MTR0 and MTR1 pins select

drive 0 drive 1 motor 0 motor 1

respectively

DR0 DR1 MTR0 and MTR1 pins contain

the encoded drive and motor information

shown in Table 4-2

PC87310 数据表(PDF) 13 Page - National Semiconductor (TI)

PC87310 数据表(HTML) 13 Page - National Semiconductor (TI)

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52

数据表下载

链接网址

PC87310 数据表(PDF) 13 Page - National Semiconductor (TI)

PC87310 数据表(HTML) 13 Page - National Semiconductor (TI)

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52

数据表 下载

链接网址

数据表下载