PC87310 datasheet(18/52 Pages) NSC

18 / 52 page

40 Functional Description (Continued)

Bit 1

This bit is the Overrun Error (OE) indicator Bit 1 indi-

cates that data in the Receiver Buffer Register was not read

by the CPU before the next character was transferred into

the Receiver Buffer Register thereby destroying the previ-

ous character The OE indicator is set to a logic 1 upon

detection of an overrun condition and reset whenever the

CPU reads the contents of the Line Status Register

Bit 2

This bit is the Parity Error (PE) indicator Bit 2 indi-

cates that the received data character does not have the

correct even or odd parity as selected by the even-parity-

select bit The PE bit is set to a logic 1 upon detection of a

parity error and is reset to a logic 0 whenever the CPU reads

the contents of the Line Status Register

Bit 3

This bit is the Framing Error (FE) indicator Bit 3 indi-

cates that the received character did not have a valid Stop

bit Bit 3 is set to a logic 1 whenever the Stop bit following

the last data bit or parity bit is a logic 0 (Spacing level) The

FE indicator is reset whenever the CPU reads the contents

of the Line Status Register The UART will try to resynchro-

nize after a framing error To do this it assumes that the

framing error was due to the next start bit so it samples this

‘‘start’’ bit twice and then takes in the ‘‘data’’

Bit 4

This bit is the Break Interrupt (BI) indicator Bit 4 is set

to a logic 1 whenever the received data input is held in the

Spacing (logic 0) state for longer than a full word transmis-

sion time (that is the total time of Start bit a data bits a

Parity a Stop bits) The BI indicator is reset whenever the

CPU reads the contents of the Line Status Register Re-

starting after a break is received requires the SIN pin to be

logical 1 for at least

bit time

Note

Bits 1 through 4 are the error conditions that produce a Receiver Line

Status interrupt whenever any of the corresponding conditions are

detected and the interrupt is enabled

Bit 5

This bit is the Transmitter Holding Register Empty

(THRE) indicator Bit 5 indicates that the UART is ready to

accept a new character for transmission In addition this bit

causes the UART to issue an interrupt to the CPU when the

Transmit Holding Register Empty Interrupt enable is set

high The THRE bit is set to a logic 1 when a character is

transferred from the Transmitter Holding Register into the

Transmitter Shift Register The bit is reset to logic 0 when-

ever the CPU loads the Transmitter Holding Register

Bit 6

This bit changes its function depending on whether

the device is operating in the XT or AT mode When operat-

ing in the AT mode this bit is the Transmitter Empty (TEMT)

indicator Bit 6 is set to a logic 1 whenever the Transmitter

Holding Register (THR) and the Transmitter Shift Register

(TSR) are both empty It is reset to a logic 0 whenever either

the THR or TSR contains a data character When operating

in the XT mode this bit is set whenever the Transmitter Shift

into the Transmit Shift Register

Bit 7

This bit is permanently set to logic 0

Note

The Line Status Register is intended for read operations only Writing

to this register is not recommended as this operation is only used for

factory testing

INTERRUPT IDENTIFICATION REGISTER

In order to provide minimum software overhead during data

character transfers the UART prioritizes interrupts into four

levels and records these in the Interrupt Identification Reg-

ister The four levels of interrupt conditions in order of prior-

ity are Receiver Line Status Received Data Ready Trans-

mitter Holding Register Empty and MODEM Status

When the CPU accesses the IIR the UART freezes all inter-

rupts and indicates the highest priority pending interrupt to

the CPU While this CPU access is occurring the UART

records new interrupts but does not change its current indi-

cation until the access is complete Table 4-4 shows the

contents of the IIR Details on each bit follow

Bit 0

This bit can be used in an interrupt environment to

indicate whether an interrupt condition is pending When bit

0 is a logic 0 an interrupt is pending and the IIR contents

may be used as a pointer to the appropriate interrupt service

routine When bit 0 is a logic 1 no interrupt is pending

Bits 1 and 2

These two bits of the IIR are used to identify

the highest priority interrupt pending as indicated in Table

4-7

Bits 3 through 7

These five bits of the IIR are always logic

TEST CONTROL REGISTER

This 8-bit write only register provides for the control of

UART test and alternate functions

Bits 0 – 3 5 – 7

These seven bits are reserved

Bit 4

This bit selects whether the Baudout (TCR4 e 1) or

SOUT (TCR4 e 0) signal will be presented at the output pin

assigned to the corresponding UART channel

INTERRUPT ENABLE REGISTER

This register enables the four types of UART interrupts

Each interrupt can individually activate the appropriate inter-

rupt (IRQ3 or IRQ4) output signal It is possible to totally

disable the interrupt system by resetting bits 0 through 3 of

the Interrupt Enable Register (IER) Similarly setting bits of

this register to a logic 1 enables the selected interrupt(s)

Disabling an interrupt prevents it from being indicated as

active in the IIR and from activating the interrupt output sig-

nal All other system functions operate in their normal man-

ner including the setting of the Line Status and MODEM

Status Registers Table 4-4 shows the contents of the IER

Details on each bit follow

Bit 0

This bit enables the Received Data Available Interrupt

when set to logic 1

Bit 1

This bit enables the Transmitter Holding Register

Empty Interrupt when set to logic 1

Bit 2

This bit enables the Receiver Line Status Interrupt

when set to logic 1

Bit 3

This bit enables the MODEM Status Interrupt when

set to logic 1

Bits 4 through 7

These four bits are always logic 0

MODEM CONTROL REGISTER

This register controls the interface with the MODEM or data

set (or a peripheral device emulating a MODEM) The con-

tents of the MODEM Control Register (MCR) are indicated

in Table 4-4 and are described below

Bit 0

This bit controls the Data Terminal Ready (DTR) out-

put When bit 0 is set to a logic 1 the DTR output is forced

to a logic 0 When bit 0 is reset to a logic 0 the DTR output

is forced to a logic 1 In local loopback mode this bit con-

trols bit 5 of the MODEM Status Register

Note

The DTR and RTS output of the UART may be applied to an EIA

inverting line driver (such as the DS1488) to obtain the proper polarity

input at the succeeding MODEM or data set

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