PC87310 datasheet(7/52 Pages) NSC

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20 Pin Descriptions

The following describes the function of all pins A low represents a logic 0 (0V nominal) and a high represents a logic 1 (a24V

nominal)

Pin Symbol

Pin Number

Description

A0–A9

(IO Address)

11 – 2

Address signals connected to these inputs select the active register

during a CPU read or write Details on each register are given in the

device section associated with that register (eg UART FDC parallel

port etc)

ACK

(Acknowledge)

This input is set low by the printer to indicate that it has received data

AEN

(Address Enable)

This input disables function selection via A0 – A9 when it is high

AFD

(Automatic Feed XT)

When this output is low the printer should automatically line feed after

each line printed This pin will be in a TRI-STATE condition 10 ns after

a zero is loaded into the corresponding Control Register bit position The

system should pull this pin high using a 47 kX resistor

BOUT1 2

(Baud Rate Output)

57 41

This multi-function output pin provides the associated serial channel

Baudout signal after data of 10 hex has been written to the TCR This

pin provides the composite serial data output signal for the associated

channel after a reset or after 00 is written to the TCR (See SOUT1 2

and CRB0 7 for further information on these pins)

BUSY

(Printer Busy)

This input is set high by the printer when it can’t accept another

character

CRPE

This multi-function pin is used to select between internal or external

(Configuration Register

default values for the Configuration Register and whether the

Program Enable)

Configuration Register can be initialized via hardware or software The

chip checks this pin during reset at that time it acts as an input If it is

low during reset the Configuration Register will default to the

complement of the CPB0 – 4 6 7 pin states If it is high the

Configuration Register will default to 00 A 47 kX (Note 1) resistor can

be used to pull this pin to the required signal level This pin will be driven

by the chip when not in reset Regardless of the initial polarity of this pin

the Configuration Register can be programmed whenever Master Reset

is inactive This pin must always have a pull up or pull down resistor

attached to it (See HCS1 and GWR for further information on pin 17

when the chip is NOT being reset)

Note 1

If the minimum reset time of 100 ns is required these resistors will have to be

reduced to k10 kX to stabilize the input signal during the reset pulse The exact resistor

value is a function of the signal capacitive loading

CRB0 – 4 6 7

41 43 44 54

These dual function pins act as inputs during reset (if CRPE e 0) to

(Configuration Register Bits)

55 16 57

determine the state of the Configuration Register bits The bits of the

Configuration Register will be the complement of these inputs A 47 kX

(Note 1) resistor can be used to pull these pins to the required signal

levels These pins will be outputs when the chip is not in reset These

pins have the following dual functions SOUT2CRB0 RTS2CRB1

DTR2CRB2 DTR1CRB3 RTS1CRB4 HCS0CRB6 SOUT1CRB7

Note 1

If the minimum reset time of 100 ns is required these resistors will have to be

reduced to k10 kX to stabilize the input signal during the reset pulse The exact resistor

value is a function of the signal capacitive loading

CTS1 2

(Clear to Send)

51 48

When low this input indicates that the MODEM or data set is ready to

exchange data The CTS signal is a MODEM status input whose

condition the CPU can test by reading bit 4 (CTS) of the MODEM Status

signal Bit 0 (DCTS) of the MODEM Status Register indicates whether

the CTS input has changed state since the previous reading of the

MODEM Status Register CTS has no effect on the transmitter

Note

Whenever the DCTS bit of the MODEM Status Register changes state an interrupt is

generated if the MODEM Status Interrupt is enabled

D0–D7

(Data Bus)

60 – 64 66 – 68

This bus contains eight TRI-STATE inputoutput lines The bus provides

bidirectional communications between this chip and the CPU Data

control words and status information are transferred via the D0 – D7

Data Bus

DAK

(DMA Acknowledge)

Active low input to acknowledge the DMA request and enable the RD

and WR inputs This signal is enabled when D3 of the Drive Control

the DMA mode

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