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CS8401A-CS 数据表(PDF) 16 Page - List of Unclassifed Manufacturers |
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CS8401A-CS 数据表(HTML) 16 Page - List of Unclassifed Manufacturers |
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16 / 34 page ![]() PIN DESCRIPTIONS Power Supply Connections VD+ - Positive Digital Power, PIN 19. Positive supply for the digital section. Nominally +5 volts. GND - Ground, PIN 18. Ground for the digital section. Audio Input Interface SCK - Serial Clock, PIN 6. Serial clock for SDATA pin which can be configured (via control register 3) as an input or output, and can sample data on the rising or falling edge. As an output, SCK will contain 32 clocks for every audio sample. As an input, it does not need to be continuous and can be up to 15 MHz. FSYNC - Frame Sync, PIN 7. Delineates the serial data and may indicate the particular channel, left or right. Also, FSYNC may be configured as an input or output. The format is based on bits in control register 3. SDATA - Serial Data, PIN 8. Audio data serial input pin. Parallel Interface CS - Chip Select, PIN 14. This input is active low and allows access to the 32 bytes of internal memory. The address bus and RD/WR must be valid while CS is low. CS8401A DATA BUS BIT 4 D4 D3 DATA BUS BIT 3 DATA BUS BIT 5 D5 D2 DATA BUS BIT 2 DATA BUS BIT 6 D6 D1 DATA BUS BIT 1 DATA BUS BIT 7 D7 D0 DATA BUS BIT 0 MASTER CLOCK MCK TXP TRANSMIT POSITIVE SERIAL DATA CLOCK SCK VD+ POWER FRAME SYNC FSYNC GND GROUND SERIAL INPUT DATA SDATA TXN TRANSMIT NEGATIVE ADDRESS BUS BIT 4 A4 RD/WR READ/WRITE SELECT ADDRESS BUS BIT 3 A3 INT INTERRUPT ADDRESS BUS BIT 2 A2 CS CHIP SELECT ADDRESS BUS BIT 1 A1 A0 ADDRESS BUS BIT 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 24 23 22 21 20 19 18 17 16 15 CS8401A 16 DS60F1 |
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