RD/WR - Read/Write, PIN 16.

If RD/WR is low when CS goes active (low), the data on the data bus is written to internal

memory. If RD/WR is high when CS goes active, the data in the internal memory is placed on

the data bus.

A4-A0 - Address Bus, PINS 9-13.

Parallel port address bus that selects the internal memory location to be read from or written to.

D0-D7 - Data Bus, PINS 21-24, 1-4.

Parallel port data bus used to check status, write control words, or write internal buffer memory.

INT - Interrupt, PIN 15.

Open drain output that can signal the state of the internal buffer memory. A 5k

Ω resistor to

VD+ is typically used to support logic gates. All bits affecting INT are maskable allowing total

control over the interrupt mechanism.

Transmitter Interface

MCK - Master Clock, PIN 5.

Clock input which defines the transmit timing. It can be configured, via control register 2, for

128, 192, 256, or 384 times the sample rate.

TXP, TXN - Differential Line Drivers, PINS 20, 17.

RS422 compatible line drivers. Drivers are pulled low when part is in reset state.

CS8401A

DS60F1

17