TLE7183F

Data Sheet

22

2.2, 2016-01-27

5.3.22

Common mode rejection ratio at

DC

CMRR =

20*Log((Vout_diff/Vin_diff) *

(Vin_CM/Vout_CM))

CMRR

80

100

–

db

–

5.3.23

CMS = 20*Log(Vout_CM/Vin_CM)

Freq =100kHz

Freq = 1MHz

Freq = 10MHz

CMS

–

62

43

33

–

db

VIN=360mV*

sin(2*

π*freq*t);

Rs=500

Ω;

Rfb=7500

Ω;

VRI=1.65/2.5V

5.3.24

Slew rate

dV/dt

3

10

–

V/µs

Gain>= 5;

5.3.25

Large signal open loop voltage gain

(DC)

80

100

–

dB

–

5.3.26

Unity gain bandwidth

GBW

10

20

–

MHz

5.3.27

Phase margin 2)

Φ

M

–

50

–

°

Gain>= 5;

5.3.28

Gain margin 2)

–12

–

db

5.3.29

Bandwidth

1.6

–

–

MHz

Gain=15;

5.3.30

Output settle time to 98% 1)

t

set

–

1

1.8

µs

Gain=15;

0.3<VO< 4.8V;

5.3.31

Output rise time 10% to 90% 1)

t

Irise

–

–

1

µs

Gain=15;

0.3<VO< 4.8V;

5.3.32

Output fall time 90% to 10%1)

t

Ifall

–

–

1

µs

Gain=15;

0.3<VO< 4.8V;

1) Input current and output amplifier characteristics:

"Output signal must be amplified and available at 2µs after input signal change (Gain 5...15)

2) Not subject to production test; specified by design

3) calculated out of 5.3.9, 5.3.10, 5.3.11 and 5.3.12

4) Without considering any offsets such as input offset voltage, internal miss match and assuming no tolerance error in

external resistors.

Electrical Characteristics - Current sense signal conditioning (cont’d)

V

(unless otherwise specified)

Pos.

Parameter

Symbol

Limit Values

Unit

Conditions

Min.

Typ.

Max.