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TLE7183SCD2 数据表(PDF) 25 Page - Infineon Technologies AG |
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TLE7183SCD2 数据表(HTML) 25 Page - Infineon Technologies AG |
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25 / 28 page ![]() Data Sheet 25 2.2, 2016-01-27 TLE7183F Application Description 6.1 Layout Guide Lines Please refer also to the simplified application example. • Three seperated bulk capacitors CB should be used - one per half bridge • Three seperated ceramic capacitors CC should be used - one per half bridge • Each of the 3 bulk capacitors CB and each of the 3 ceramic capacitors CC should be assigned to one of the half bridges and should be placed very close to it • The components within one half bridge should be placed close to each other: high side MOSFET, low side MOSFET, bulk capacitor CB and ceramic capacitor CC (CB and CC are in parallel) and the shunt resistor form a loop that should be as small and tight as possible. The traces should be short and wide • The three half bridges can be seperated; yet, when there is one common GND referenced shunt resistor for the three half bridges the sources of the three low side MOSFETs should be close to each other and close to the common shunt resistor • VDH is the sense pin used for short circuit detection; VDH should be routed (via Rvdh) to the common point of the drains of the high side MOSFETs to sense the voltage present on drain high side • CB2 is the buffer capacitor of charge pump 2; its negative terminal should be routed to the common point of the drains of the high side MOSFETs as well - this connection should be low inductive / resistive • Additional R-C snubber circuits (R and C in series) can be placed to attenuate/suppress oscillations during switching of the MOSFETs, there may be one or two snubber circuits per half bridge, R (several Ohm) and C (several nF) must be low inductive in terms of routing and packaging (ceramic capacitors) • the exposed pad on the backside of the VQFN should be connected to GND 6.2 Further Application Information • For further information you may contact http://www.infineon.com/ |
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