DS00002142A-page 21

USB3250

7.3

Clock and Data Recovery Circuit

This block consists of the Clock and Data Recovery Circuit and the Elasticity Buffer. The Elasticity Buffer is used to com-

pensate for differences between the transmitting and receiving clock domains. The USB 2.0 specification defines a max-

imum clock error of ±1000ppm of drift.

7.4

TX Logic

This block receives parallel data bytes placed on the DATA bus and performs the necessary transmit operations. These

operations include parallel to serial conversion, bit stuffing and NRZI encoding. Upon valid assertion of the proper TX

control lines by the SIE and TX State Machine, the TX LOGIC block will synchronously shift, at either the FS or HS rate,

the data to the FS/HS TX block to be transmitted on the USB cable. Data transmit timing is shown in Figure 7-4.

FIGURE 7-4:

TRANSMIT TIMING FOR A DATA PACKET (8-BIT MODE)

FIGURE 7-5:

TRANSMIT TIMING FOR 16-BIT DATA, EVEN BYTE COUNT

PID

DATA

SYNC

DATA

DATA

DATA

CRC

CRC

EOP

DATA

DATA

DATA

CRC

CRC

DATA

PID

CLK60

TXVALID

TXDATA[7:0]

TXREADY

DP/DM

CLK30

DATA[7:0]

TXREADY

TXVALID

DP/DM

PID

DATA

SYNC

DATA

DATA

DATA

DATA

CRC

CRC

PID

DATA[15:8]

DATA (0)

DATA (1)

DATA (2)

DATA (3)

DATA (4)

CRC (HI)

01

2

3

4

HI

VALIDH

CRC (LO)

EOP

LO