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USB3250 数据表(PDF) 27 Page - Microchip Technology

部件名 USB3250
功能描述  Hi-Speed USB Device Transceiver with UTMI Interface
PDF  46 Pages
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制造商  MICROCHIP [Microchip Technology]
网页  http://www.microchip.com
标志 MICROCHIP - Microchip Technology

USB3250 数据表(HTML) 27 Page - Microchip Technology

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2013 - 2016 Microchip Technology Inc.
DS00002142A-page 27
USB3250
8.0
APPLICATION NOTES
The following sections consist of select functional explanations to aid in implementing the PHY into a system. For com-
plete description and specifications consult the USB 2.0 Transceiver Macrocell Interface Specification and Universal
Serial Bus Specification Revision 2.0.
8.1
Linestate
The voltage thresholds that the LINESTATE[1:0] signals use to reflect the state of DP and DM depend on the state of
XCVRSELECT. LINESTATE[1:0] uses HS thresholds when the HS transceiver is enabled (XCVRSELECT = 0) and FS
thresholds when the FS transceiver is enabled (XCVRSELECT = 1). There is not a concept of variable single-ended
thresholds in the USB 2.0 specification for HS mode.
The HS receiver is used to detect Chirp J or K, where the output of the HS receiver is always qualified with the Squelch
signal. If squelched, the output of the HS receiver is ignored. In the USB3250, as an alternative to using variable thresh-
olds for the single-ended receivers, the following approach is used.
In HS mode, 3ms of no USB activity (IDLE state) signals a reset. The SIE monitors LINESTATE[1:0] for the IDLE state.
To minimize transitions on LINESTATE[1:0] while in HS mode, the presence of !Squelch is used to force LINES-
TATE[1:0] to a J state.
8.2
OPMODES
The OPMODE[1:0] pins allow control of the operating modes.
The OPMODE[1:0] signals are normally changed only when the transmitter and the receiver are quiescent, i.e. when
entering a test mode or for a device initiated resume.
When using OPMODE[1:0] = 10 (state 2), OPMODES are set, and then 5 60MHz clocks later, TXVALID is asserted. In
this case, the SYNC and EOP patterns are not transmitted.
TABLE 8-1:
LINESTATE STATES
State of DP/DM Lines
LINESTATE[1:0]
Full Speed
XCVRSELECT =1
TERMSELECT=1
High Speed
XCVRSELECT =0
TERMSELECT=0
Chirp Mode
XCVRSELECT =0
TERMSELECT=1
LS[1]
LS[0]
0
0
SE0
Squelch
Squelch
0
1
J
!Squelch
!Squelch & HS
Differential Receiver
Output
1
0
K
Invalid
!Squelch & !HS
Differential Receiver
Output
1
1
SE1
Invalid
Invalid
TABLE 8-2:
OPERATIONAL MODES
Mode[1:0]
State#
State Name
Description
00
0
Normal Operation
Transceiver operates with normal USB data encoding and
decoding
01
1
Non-Driving
Allows the transceiver logic to support a soft disconnect
feature which tri-states both the HS and FS transmitters,
and removes any termination from the USB making it
appear to an upstream port that the device has been
disconnected from the bus
10
2
Disable Bit Stuffing
and NRZI encoding
Disables bitstuffing and NRZI encoding logic so that 1's
loaded from the TXDATA bus become 'J's on the DP/DM
and 0's become 'K's
11
3
Reserved
N/A



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