USB3250

DS00002142A-page 20

7.2

System Clocking

This block connects to either an external 12MHz crystal or an external clock source and generates a 480MHz multi-

phase clock. The clock is used in the CRC block to over-sample the incoming received data, resynchronize the transmit

data, and is divided down to a 30MHz or 60MHz version (CLKOUT) which acts as the system byte clock. The PLL block

also outputs a clock valid signal to the other parts of the transceiver when the clock signal is stable. All UTMI signals

are synchronized to the CLKOUT output. The behavior of the CLKOUT is as follows:

• Produce the first CLKOUT transition no later than 5.6ms after negation of SUSPENDN. The CLKOUT signal fre-

quency error is less than 10% at this time.

• The CLKOUT signal will fully meet the required accuracy of ±500ppm no later than 1.4ms after the first transition

of CLKOUT.

In HS mode there is one CLKOUT cycle per byte time. The frequency of CLKOUT does not change when the Macrocell

is switched between HS to FS modes. In FS mode (8-bit mode) there are 5 CLK60 cycles per FS bit time, typically 40

CLK60 cycles per FS byte time. If a received byte contains a stuffed bit then the byte boundary can be stretched to 45

CLK60 cycles, and two stuffed bits would result in a 50 CLK60 cycles.

Figure 7-2 shows the relationship between CLK60 and the transmit data transfer signals in FS mode. TXREADY is only

asserted for one CLK60 per byte time to signal the SIE that the data on the TXDATA lines has been read by the Mac-

rocell. The SIE may hold the data on the TXDATA lines for the duration of the byte time. Transitions of TXVALID must

meet the defined setup and hold times relative to CLK60.

Figure 7-3 shows the relationship between CLK60 and the receive data control signals in FS mode. RXACTIVE "frames"

a packet, transitioning only at the beginning and end of a packet. However transitions of RXVALID may take place any

time 8 bits of data are available. Figure 7-3 also shows how RXVALID is only asserted for one CLKOUT cycle per byte

time even though the data may be presented for the full byte time. The XCVRSELECT signal determines whether the

HS or FS timing relationship is applied to the data and control signals.

FIGURE 7-2:

FS CLK RELATIONSHIP TO TRANSMIT DATA AND CONTROL SIGNALS (8-BIT

MODE)

FIGURE 7-3:

FS CLK RELATIONSHIP TO RECEIVE DATA AND CONTROL SIGNALS (8-BIT

MODE)

CLKOUT

TXDATA[7:0]

TXVALID

TXREAD

Y

Don'

t

Care

DATA

3

PI

D

DATA

4

DATA

1

DATA

2

DATA(n+1)

DATA(n+2)

CLK60

RXACTIVE

RXDATA[7:0]

RXVALID

DATA(n)