SST25VF080B datasheet(16/32 Pages) MICROCHIP

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SST25VF080B

DS20005045C-page 16

 2015 Microchip Technology Inc.

4.4.14

WRITE-STATUS-REGISTER (WRSR)

The Write-Status-Register instruction writes new val-

ues to the BP3, BP2, BP1, BP0, and BPL bits of the sta-

tus register. CE# must be driven low before the

command sequence of the WRSR instruction is

entered and driven high before the WRSR instruction is

executed. See Figure 4-17 for EWSR or WREN and

WRSR instruction sequences.

Executing the Write-Status-Register instruction will be

ignored when WP# is low and BPL bit is set to “1”.

When the WP# is low, the BPL bit can only be set from

“0” to “1” to lock-down the status register, but cannot be

reset from “1” to “0”. When WP# is high, the lock-down

function of the BPL bit is disabled and the BPL, BP0,

and BP1 and BP2 bits in the status register can all be

changed. As long as BPL bit is set to 0 or WP# pin is

driven high (VIH) prior to the low-to-high transition of the

CE# pin at the end of the WRSR instruction, the bits in

the status register can all be altered by the WRSR

instruction. In this case, a single WRSR instruction can

set the BPL bit to “1” to lock down the status register as

well as altering the BP0, BP1, and BP2 bits at the same

time. See Table 4-1 for a summary description of WP#

and BPL functions.

FIGURE 4-17:

ENABLE-WRITE-STATUS-REGISTER (EWSR) OR WRITE-ENABLE (WREN) AND

WRITE-STATUS-REGISTER (WRSR) SEQUENCE

4.4.15

JEDEC READ-ID

The JEDEC Read-ID instruction identifies the device as

SST25VF080B and the manufacturer as Microchip.

The device information can be read from executing the

8-bit command, 9FH. Following the JEDEC Read-ID

instruction, the 8-bit manufacturer’s ID, BFH, is output

from the device. After that, a 16-bit device ID is shifted

out on the SO pin. Byte 1, BFH, identifies the manufac-

turer as Microchip. Byte 2, 25H, identifies the memory

type as SPI Serial Flash. Byte 3, 8EH, identifies the

device as SST25VF080B. The instruction sequence is

shown in Figure 4-18. The JEDEC Read ID instruction

is terminated by a low to high transition on CE# at any

time during data output.

FIGURE 4-18:

JEDEC READ-ID SEQUENCE

1296 EWSR.0

MODE 3

HIGH IMPEDANCE

MODE 0

STATUS

7 6 5 4321 0

MSB

MODE 3

SCK

CE#

MODE 0

50 or 06

0 1 2 3 4 5 6 7

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15

TABLE 4-5:

JEDEC READ-ID DATA

Manufacturer’s ID

Device ID

Memory Type

Memory Capacity

Byte1

Byte 2

Byte 3

BFH

25H

8EH

1296 JEDECID.1

CE#

SCK

012345678

HIGH IMPEDANCE

15 16

28 29 30 31

MODE 3

MODE 0

MSB

9 10111213

1718

19 20 21 22 23

24 25 26 27

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