STM32F413XG datasheet(115/207 Pages) STMICROELECTRONICS

部件名	STM32F413XG

功能描述	ARM-Cortex-M4 32b MCUFPU, 125 DMIPS, up to 1.5MB Flash, 320KB RAM, USB OTG FS, 1 ADC, 2 DACs, 2 DFSDMs

PDF	207 Pages

Scroll/Zoom	100%

制造商	STMICROELECTRONICS [STMicroelectronics]

网页	http://www.st.com

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115 / 207 page

DocID029162 Rev 2

115/207

STM32F413xG/H

Electrical characteristics

174

Table 47. PLLI2S (audio PLL) characteristics

Symbol

Parameter

Conditions

Min

Typ

Max

Unit

fPLL_IN

PLL input clock(1)

-0.95(2)

12.10

MHz

fPLLI2SQ_OUT

48 MHz PLLI2SQ

multiplier output clock

fPLLI2SR_OUT

PLLI2SR multiplier output clock

for I2S and SAI

216

fVCO_OUT

PLLI2S VCO output

100

432

tLOCK

PLLI2S lock time

VCO freq = 100 MHz

200

µs

VCO freq = 432 MHz

100

300

Jitter(3)

Master I2S clock jitter

Cycle to cycle at

12.288 MHz on

48 kHz period,

N=432, R=5

RMS

peak

±280

Average frequency of

12.288 MHz

N = 432, R = 5

on 1000 samples

-90

WS I2S clock jitter

Cycle to cycle at 48 KHz

on 1000 samples

400

IDD(PLLI2S)(4)

PLLI2S power consumption on

VDD

VCO freq = 100 MHz

VCO freq = 432 MHz

0.15

0.45

0.40

0.75

IDDA(PLLI2S)(4)

PLLI2S power consumption on

VDDA

VCO freq = 100 MHz

VCO freq = 432 MHz

0.30

0.55

0.40

0.85

1. Take care of using the appropriate division factor M to have the specified PLL input clock values.

2. Guaranteed by design.

3. Value given with main PLL running.

4. Guaranteed by characterization.

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