STM32F413XG datasheet(21/207 Pages) STMICROELECTRONICS

部件名	STM32F413XG

功能描述	ARM-Cortex-M4 32b MCUFPU, 125 DMIPS, up to 1.5MB Flash, 320KB RAM, USB OTG FS, 1 ADC, 2 DACs, 2 DFSDMs

PDF	207 Pages

Scroll/Zoom	100%

制造商	STMICROELECTRONICS [STMicroelectronics]

网页	http://www.st.com

标志

21 / 207 page

DocID029162 Rev 2

21/207

STM32F413xG/H

Functional overview

3.7

Embedded SRAM

All devices embed 320 Kbytes of system SRAM which can be accessed (read/write) at CPU

clock speed with 0 wait states.

3.8

Multi-AHB bus matrix

The 32-bit multi-AHB bus matrix interconnects all the masters (CPU, DMAs) and the slaves

(Flash memory, RAM, AHB and APB peripherals) and ensures a seamless and efficient

operation even when several high-speed peripherals work simultaneously.

Figure 5. Multi-AHB matrix

CPU can access SRAM1 memory via S-bus, when SRAM1 is mapped at the address range:

0x2000 0000 to 0x2003 FFFF.

CPU can access SRAM2 memory via S-bus, when SRAM2 is mapped at the address range:

0x2004 0000 to 0x2004 FFFF.

CPU can access SRAM1 memory via I-bus and D-bus, when SRAM1 is remapped at

address 0x0000 0000 either by booting from RAM memory or by the remap mode.

CPU can access SRAM2 memory via I-bus and D-bus, when SRAM2 is mapped at the

address range: 0x1000 0000 to 0x1000 FFFF.

Performance boosts up, when the CPU access SRAM memory via the I-bus.

STM32F413XG 数据表(PDF) 21 Page - STMicroelectronics