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STM32F413XG 数据表(PDF) 41 Page - STMicroelectronics |
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STM32F413XG 数据表(HTML) 41 Page - STMicroelectronics |
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41 / 207 page ![]() DocID029162 Rev 2 41/207 STM32F413xG/H Functional overview 42 The main USB OTG FS features are: • Combined Rx and Tx FIFO size of 320 × 35 bits with dynamic FIFO sizing • Support of session request protocol (SRP) and host negotiation protocol (HNP) • 6 bidirectional endpoints • 12 host channels with periodic OUT support • HNP/SNP/IP inside (no need for any external resistor) • For OTG/Host modes, a power switch is needed when bus-powered devices are connected • Link Power Management (LPM) • Battery Charging Detection (BCD) supporting DCP, CDP and SDP 3.34 Random number generator (RNG) All devices embed an RNG that delivers 32-bit random numbers generated by an integrated analog circuit. 3.35 General-purpose input/outputs (GPIOs) Each of the GPIO pins can be configured by software as output (push-pull or open-drain, with or without pull-up or pull-down), as input (floating, with or without pull-up or pull-down) or as peripheral alternate function. Most of the GPIO pins are shared with digital or analog alternate functions. All GPIOs are high-current-capable and have speed selection to better manage internal noise, power consumption and electromagnetic emission. The I/O configuration can be locked if needed by following a specific sequence in order to avoid spurious writing to the I/Os registers. Fast I/O handling allowing maximum I/O toggling up to 100 MHz. 3.36 Analog-to-digital converter (ADC) One 12-bit analog-to-digital converter is embedded and shares up to 16 external channels, performing conversions in the single-shot or scan mode. In scan mode, automatic conversion is performed on a selected group of analog inputs. The ADC can be served by the DMA controller. An analog watchdog feature allows very precise monitoring of the converted voltage of one, some or all selected channels. An interrupt is generated when the converted voltage is outside the programmed thresholds. To synchronize A/D conversion and timers, the ADCs could be triggered by any of TIM1, TIM2, TIM3, TIM4 or TIM5 timer. 3.37 Digital to analog converter (DAC) The two 12-bit buffered DAC channels can be used to convert two digital signals into two analog voltage signal outputs. This digital interface supports the following features: • Two DAC output channels |
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